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ORCIDHiroshi Fuketa
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2020 – today
- 2024
[j26]Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda
, Takahiro Mori:
Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs. IEEE Access 12: 12458-12464 (2024)- [j25]Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki:
Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. IEEE Access 12: 102470-102480 (2024) - 2023
- [j24]Hiroshi Oka, Takumi Inaba, Shunsuke Shitakata, Kimihiko Kato, Shota Iizuka, Hidehiro Asai, Hiroshi Fuketa, Takahiro Mori:
Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality. IEEE Access 11: 121567-121573 (2023) - [j23]Hiroshi Fuketa:
Lookup Table-Based Computing-in-Memory Macro Approximating Dot Products Without Multiplications for Energy-Efficient CNN Inference. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3954-3963 (2023) - [j22]Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori:
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5220-5228 (2023) - [c30]Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori:
Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j21]Hiroshi Fuketa:
Time-Delay-Neural-Network-Based Audio Feature Extractor for Ultra-Low Power Keyword Spotting. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 334-338 (2022) - [c29]Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori:
A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution. VLSI Technology and Circuits 2022: 234-235 - 2021
- [j20]Hiroshi Fuketa, Kunio Uchiyama:
Edge Artificial Intelligence Chips for the Cyberphysical Systems Era. Computer 54(1): 84-88 (2021) - [j19]Hiroshi Fuketa:
Ultra-Low Power Hand Gesture Sensor Using Electrostatic Induction. Sensors 21(24): 8268 (2021) - 2020
- [i1]Hiroshi Fuketa, Yukinori Morita:
Neural ODE with Temporal Convolution and Time Delay Neural Networks for Small-Footprint Keyword Spotting. CoRR abs/2008.00209 (2020)
2010 – 2019
- 2019
- [c28]Hiroshi Fuketa, Yukinori Morita:
Ultra-low Power Human Motion Detection Sensor using Electrostatic Induction and Demonstration of Contactless Remote Light Switch. GCCE 2019: 951-952 - 2018
- [c27]Shin-ichi O'Uchi, Hiroshi Fuketa, Tsutomu Ikegami, Wakana Nogami, Takashi Matsukawa, Tomohiro Kudoh, Ryousei Takano:
Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format. ISCAS 2018: 1-5 - 2017
- [j18]Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. IEICE Trans. Electron. 100-C(4): 349-358 (2017) - [j17]Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa:
Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 392-396 (2017) - [j16]Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa:
A 0.3-V 1-µW Super-Regenerative Ultrasound Wake-Up Receiver With Power Scalability. IEEE Trans. Circuits Syst. II Express Briefs 64-II(9): 1027-1031 (2017) - [j15]Hiroshi Fuketa, Shin-ichi O'Uchi, Takashi Matsukawa:
A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2007-2016 (2017) - [c26]Jan Genoe, Hiroshi Fuketa, Eugenio Cantatore:
Session 15 overview: Innovations in technologies and circuits. ISSCC 2017: 254-255 - 2016
- [j14]Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster. IEEE J. Solid State Circuits 51(2): 496-508 (2016) - 2015
- [j13]Shunta Iguchi, Pyungwoo Yeon, Hiroshi Fuketa, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya:
Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 938-947 (2015) - [c25]Dan Luo, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Makoto Takamiya, Takayasu Sakurai:
Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit. ECCTD 2015: 1-4 - [c24]Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. ESSCIRC 2015: 249-252 - [c23]Yoshitaka Yamauchi, Yuki Yanagihara, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications. ICICDT 2015: 1-4 - [c22]Hiroshi Fuketa, Masamune Hamamatsu, Tomoyuki Yokota, Wakako Yukita, Teruki Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. ISSCC 2015: 1-3 - 2014
- [j12]Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE J. Solid State Circuits 49(2): 536-544 (2014) - [j11]Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control. IEEE Trans. Biomed. Circuits Syst. 8(6): 824-833 (2014) - [c21]Hiroshi Fuketa, Youichi Momiyama, Atsushi Okamoto, Tsuyoshi Sakata, Makoto Takamiya, Takayasu Sakurai:
An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting. ESSCIRC 2014: 263-266 - [c20]Hiroshi Fuketa, Kazuaki Yoshioka, Tomoyuki Yokota, Wakako Yukita, Mari Koizumi, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance. ISSCC 2014: 490-491 - [c19]Makoto Takamiya, Hiroshi Fuketa, Koichi Ishida, Tomoyuki Yokota, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai:
Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications. MWSCAS 2014: 829-832 - [c18]Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator. VLSIC 2014: 1-2 - 2013
- [j10]Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. IEEE J. Solid State Circuits 48(1): 255-264 (2013) - [j9]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits 48(8): 1986-1994 (2013) - [j8]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1175-1179 (2013) - [c17]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Variation-aware subthreshold logic circuit design. ASICON 2013: 1-4 - [c16]Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai:
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. ISQED 2013: 210-215 - [c15]Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. ISSCC 2013: 104-105 - [c14]Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC 2013: 436-437 - [c13]Hiroshi Fuketa, Koichi Ishida, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Large-area and flexible sensors with organic transistors. IWASI 2013: 87-90 - 2012
- [j7]Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 918-921 (2012) - [j6]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 333-343 (2012) - [j5]Xin Zhang, Koichi Ishida, Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai:
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1876-1880 (2012) - [c12]Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC 2012: 1-4 - [c11]Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai:
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. ISQED 2012: 586-591 - [c10]Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai:
Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. ISSCC 2012: 308-310 - [c9]Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC 2012: 486-488 - 2011
- [j4]Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye:
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 299-303 (2011) - [c8]Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. DAC 2011: 984-989 - [c7]Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED 2011: 21-26 - [c6]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. ISLPED 2011: 163-168 - 2010
- [j3]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1118-1129 (2010) - [c5]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC 2010: 361-362
2000 – 2009
- 2009
- [j2]Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Trans. Electron. 92-C(2): 281-285 (2009) - [j1]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3094-3102 (2009) - [c4]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC 2009: 266-271 - [c3]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC 2009: 215-218 - 2008
- [c2]Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390 - [c1]Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8
Coauthor Index
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