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ORCIDNihar R. Mohapatra
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2020 – today
- 2025
[j5]Ramandeep Kaur, Nihar R. Mohapatra:
Exploring the impact of sheet thickness scaling on Nanosheet FET gate electrostatics using k.p based simulations. Microelectron. J. 156: 106480 (2025)- 2024
- [j4]Rutu Patel
, Nihar R. Mohapatra:
On the improved RF performance of step field plate LDMOS transistor. Microelectron. J. 148: 106210 (2024) - [c22]Nishant Kumar, Hari Shanker Gupta, Anuj Srivastava, Nihar Ranjan Mohapatra:
A Programmable and Adaptive Dead-Time Controller for Low-Offset Output Generation for Cryo-Cooler Drive Applications. ISCAS 2024: 1-5 - [c21]Om Maheshwari, Dev Vyas, Nihar Ranjan Mohapatra:
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs. VLSID 2024: 19-24 - 2023
- [c20]Nishant Kumar, Hari Shanker Gupta, Nilesh M. Desai, Nihar Ranjan Mohapatra:
Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics. APCCAS 2023: 197-201 - [i2]Shubham Patil, Anand Sharma, Gaurav R, Abhishek Kadam, Ajay Kumar Singh, Sandip Lashkare, Nihar Ranjan Mohapatra, Udayan Ganguly:
Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron. CoRR abs/2306.11640 (2023) - 2022
- [j3]Satyajit Mohapatra, Nihar Ranjan Mohapatra:
Dispersion in Placement: Quantification and Insights. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2380-2392 (2022) - [c19]Anuj Srivastava, Nishant Kumar, Nihar Ranjan Mohapatra, Hari Shankar Gupta:
High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics. VDAT 2022: 150-157 - 2021
- [c18]Kaushal Kumari Neeraj, Nihar Ranjan Mohapatra:
Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis. VDAT 2021: 1-4 - 2020
- [j2]Satyajit Mohapatra, Nihar Ranjan Mohapatra:
Gradient Error Compensation in SC-MDACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4359-4374 (2020) - [c17]Satyajit Mohapatra, Nihar Ranjan Mohapatra:
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD). VLSID 2020: 72-77
2010 – 2019
- 2019
- [c16]Sarath Chandran G. M, Mohit D. Ganeriwala, Nihar Ranjan Mohapatra:
Capacitance and Surface Potential Model for III-V Double-Gate FET. ISDCS 2019: 1-5 - [c15]Yadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra:
Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications. VDAT 2019: 590-604 - [c14]Amratansh Gupta, Mohit Ganeriwala, Nihar Ranjan Mohapatra:
An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors. VLSID 2019: 163-167 - [c13]Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya:
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. VLSID 2019: 305-310 - [i1]Tanmay Chavan, Sangya Dutta, Nihar R. Mohapatra, Udayan Ganguly:
Band-to-Band Tunneling based Ultra-Energy Efficient Silicon Neuron. CoRR abs/1902.09726 (2019) - 2018
- [c12]Tanmay Chavan, S. Dutta, Nihar R. Mohapatra, Udayan Ganguly:
An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology. DRC 2018: 1-2 - [c11]Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra:
Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS. ISVLSI 2018: 175-180 - [c10]Satyajit Mohapatra, Nihar Ranjan Mohapatra:
The HotSpot Compensation in High Speed Data Converters. MWSCAS 2018: 396-399 - 2017
- [c9]Apoorva Ojha, Nihar R. Mohapatra:
Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model. ESSDERC 2017: 200-203 - [c8]Jatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra:
Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices. VDAT 2017: 56-61 - [c7]Ashish Soni, Abhijit Umap, Nihar R. Mohapatra:
Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs. VDAT 2017: 227-238 - [c6]Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra:
A 64b/66b Line Encoding for High Speed Serializers. VLSID 2017: 303-308 - 2016
- [c5]Hari Shanker Gupta, Satyajit Mohapatra, Nihar R. Mohapatra, Dinesh Kumar Sharma:
Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array. ISQED 2016: 462-467 - [c4]Apoorva Ojha, Narendra Parihar, Nihar R. Mohapatra:
Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors. VLSID 2016: 323-327
2000 – 2009
- 2003
- [c3]Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao:
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. VLSI Design 2003: 99-104 - [c2]D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao:
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. VLSI Design 2003: 128- - 2001
- [j1]Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao:
Sub-100 nm CMOS circuit performance with high-K gate dielectrics. Microelectron. Reliab. 41(7): 1045-1048 (2001) - [c1]Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao:
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. VLSI Design 2001: 479-
Coauthor Index
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