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ORCIDToshiaki Kirihata
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2010 – 2019
- 2018
[j16]Balaji Jayaraman
, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. IEEE J. Solid State Circuits 53(3): 949-960 (2018)- [c12]Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata:
14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. VLSI Circuits 2018: 87-88 - 2016
- [j15]Toshiaki Kirihata, John Golz, Matthew R. Wordeman, Pooja Batra, Gary W. Maier, Norman Robson, Troy L. Graves-abe, Daniel Berger, Subramanian S. Iyer:
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 373-384 (2016) - [j14]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer:
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits 51(1): 230-239 (2016) - [c11]Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2 - 2015
- [c10]Chandrasekharan Kothandaraman, X. Chen, Dan Moy, Dallas Lea, Sami Rosenblatt, Faraz Khan, Derek Leu, Toshiaki Kirihata, D. Ioannou, Giuseppe La Rosa, Jeffrey B. Johnson, Norman Robson, Subramanian S. Iyer:
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications. IRPS 2015: 2 - 2014
- [c9]Toshiaki Kirihata, Dinesh Somasekhar:
Advanced memory topics. CICC 2014: 1 - 2013
- [j13]Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM. IEEE J. Solid State Circuits 48(4): 940-947 (2013) - [j12]Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM. IEEE J. Solid State Circuits 48(11): 2934-2943 (2013) - [c8]Koji Nii, Toshiaki Kirihata:
Advanced memory topics. CICC 2013: 1 - 2012
- [c7]Daniel Fainstein, Sami Rosenblatt, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer:
Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM. VLSIC 2012: 146-147 - 2011
- [j11]John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits 46(1): 64-75 (2011) - [c6]Subramanian S. Iyer, Toshiaki Kirihata, John E. Barth Jr.:
Three Dimensional integration - Considerations for memory applications. CICC 2011: 1-7
2000 – 2009
- 2009
- [j10]Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer:
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44(4): 1216-1226 (2009) - 2008
- [j9]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43(1): 86-95 (2008) - [c5]Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata:
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. ESSCIRC 2008: 66-69 - [c4]Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer:
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. ISSCC 2008: 406-407 - 2007
- [c3]Norman Robson, John Safran, Chandrasekharan Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Alan Leslie, Dan Moy, Toshiaki Kirihata, Subramanian S. Iyer:
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips. CICC 2007: 799-804 - [c2]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC 2007: 486-617 - 2005
- [j8]Toshiaki Kirihata, Paul C. Parries, David R. Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Matt Wordeman, Subramanian S. Iyer:
An 800-MHz embedded DRAM with a concurrent refresh mode. IEEE J. Solid State Circuits 40(6): 1377-1387 (2005) - 2000
- [j7]Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman:
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. IEEE J. Solid State Circuits 35(5): 713-718 (2000)
1990 – 1999
- 1999
- [j6]Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman:
A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34(11): 1580-1588 (1999) - 1998
- [j5]Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl:
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. IEEE J. Solid State Circuits 33(11): 1711-1719 (1998) - 1997
- [j4]Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik:
Flexible test mode approach for 256-Mb DRAM. IEEE J. Solid State Circuits 32(10): 1525-1534 (1997) - [c1]W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi:
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285 - 1996
- [j3]Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao:
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31(4): 558-566 (1996) - [j2]Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31(4): 567-574 (1996) - 1995
- [j1]Sang H. Dhong, Masahiro Tanaka, Steven W. Tomashot, Toshiaki Kirihata:
A low-noise TTL-compatible CMOS off-chip driver circuit. IBM J. Res. Dev. 39(1-2): 105-112 (1995)
Coauthor Index
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