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ORCIDJames B. Kuo
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2010 – 2019
- 2014
[c18]Chen-Bo Hsu, Young Sik Hong, James B. Kuo:
MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit. ICECS 2014: 60-63- [c17]Gregory J. Y. Lin, Chienbo B. Hsu, James B. Kuo:
Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs. ISCAS 2014: 1740-1743 - [c16]Chen-Bo Hsu, James B. Kuo:
MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits. ISIC 2014: 328-331 - [c15]D. H. Lung, S. K. Hu, James B. Kuo, D. Chen, Y. J. Chen:
Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device. ISIC 2014: 412-415 - [c14]Chen-Bo Hsu, James B. Kuo:
Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS. MWSCAS 2014: 921-924 - 2011
- [c13]Henry X. F. Huang, Steven R. S. Shen, James B. Kuo:
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique. PATMOS 2011: 143-151 - 2010
- [j12]H. J. Hung, James B. Kuo, D. Chen, Chih-Sheng Yeh:
Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect. Microelectron. Reliab. 50(5): 607-609 (2010) - [c12]Chih-Hsiang Lin, James B. Kuo:
Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications. ISCAS 2010: 3833-3836
2000 – 2009
- 2009
- [c11]Chih-Hsiang Lin, James B. Kuo:
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. PATMOS 2009: 127-135 - 2007
- [c10]Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki:
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. PATMOS 2007: 453-462 - 2005
- [c9]James B. Kuo:
Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited. IWSOC 2005: 143-148 - 2004
- [c8]Hung-Pin Chen, James B. Kuo:
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI. ICECS 2004: 175-178 - 2003
- [c7]P. C. Chen, James B. Kuo:
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. ISCAS (5) 2003: 441-444 - 2002
- [j11]Perng-Fei Lin, James B. Kuo:
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. IEEE J. Solid State Circuits 37(10): 1307-1317 (2002) - 2001
- [j10]Perng-Fei Lin, James B. Kuo:
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. IEEE J. Solid State Circuits 36(4): 666-675 (2001) - [j9]S. C. Liu, F. A. Wu, James B. Kuo:
A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. IEEE J. Solid State Circuits 36(4): 712-716 (2001) - 2000
- [c6]Bo-Ting Wang, James B. Kuo:
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. ISCAS 2000: 733-736
1990 – 1999
- 1998
- [c5]J. H. Lou, James B. Kuo:
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder. ICECS 1998: 171-174 - 1997
- [j8]J. H. Lou, James B. Kuo:
A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. IEEE J. Solid State Circuits 32(1): 119-121 (1997) - 1996
- [j7]Y. G. Chen, James B. Kuo:
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 256-258 (1996) - 1995
- [j6]James B. Kuo, K. W. Su, J. H. Lou, S. S. Chen, C. S. Chiang:
A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology. IEEE J. Solid State Circuits 30(1): 73-75 (1995) - [j5]James B. Kuo, K. W. Su, J. H. Lou:
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. IEEE J. Solid State Circuits 30(8): 950-954 (1995) - 1994
- [c4]James B. Kuo, K. W. Su, J. H. Lou:
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. ISCAS 1994: 323-326 - [c3]James B. Kuo, B. Y. Chen, Mark W. Mao:
A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI. ISCAS 1994: 331-334 - 1993
- [c2]Mark W. Mao, B. Y. Chen, James B. Kuo:
A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique. ISCAS 1993: 1967-1970 - [c1]James B. Kuo, Hung-Pin Chen, H. J. Huang:
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. ISCAS 1993: 2027-2030 - 1992
- [j4]Mark W. Mao, James B. Kuo:
A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition. Neural Networks 5(5): 835-841 (1992) - [j3]H.-C. Chow, W.-S. Feng, James B. Kuo:
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(12): 1522-1528 (1992)
1980 – 1989
- 1989
- [j2]James B. Kuo, G. P. Rosseel, Robert W. Dutton:
Two-dimensional analysis of a merged BiPMOS device. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(8): 929-932 (1989) - [j1]James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley:
Two-dimensional transient analysis of a collector-up ECL inverter. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10): 1038-1045 (1989)
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