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2010 – 2019
- 2015
[j2]Kiichi Niitsu
, Yusuke Osawa, Naohiro Harigai, Daiki Hirabayashi, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
A CMOS PWM Transceiver Using Self-Referenced Edge Detection. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1145-1149 (2015)- 2013
- [j1]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai:
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J. Electron. Test. 29(6): 879-892 (2013) - [c5]Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. ASP-DAC 2013: 103-104 - 2012
- [c4]Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi:
Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS 2012: 671-674 - [c3]Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS. ASP-DAC 2012: 553-554 - [c2]Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. VLSIC 2012: 142-143 - 2011
- [c1]Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi:
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements. ISOCC 2011: 146-149
Coauthor Index
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