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2020 – today
- 2024
[j8]Hsiang Huang, Yung-Yuan Chen
:
Development of an Effective Corruption-Related Scenario-Based Testing Approach for Robustness Verification and Enhancement of Perception Systems in Autonomous Driving. Sensors 24(1): 301 (2024)- 2021
- [j7]Kuen-Long Lu, Yung-Yuan Chen:
SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment. J. Circuits Syst. Comput. 30(14): 2150254:1-2150254:38 (2021) - [c23]Kuen-Long Lu, Yung-Yuan Chen:
Model-based design, analysis and assessment framework for safety-critical systems. DSN (Supplements) 2021: 25-26 - [i1]Zong-Ming Lin, Cheng-Yang Chang, Chin-Yu Hu, Yung-Yuan Chen:
Intelligent Traffic Control System by Using Image Information. CoRR abs/2109.10181 (2021) - 2020
- [c22]Hsiang Huang, Kuan-Chung Chen, Po-Yi Li, Yung-Yuan Chen:
Analysis of the Effect of Automotive Ethernet Camera Image Quality on Object Detection Models. ICAIIC 2020: 21-26 - [c21]Yan-Xun LU, Yung-Yuan Chen, Wen-Nan Fang:
Automotive Ethernet-Based Black Box System. ICAIIC 2020: 392-397
2010 – 2019
- 2019
- [c20]Kuen-Long Lu, Yung-Yuan Chen:
ISO 26262 ASIL-Oriented Hardware Design Framework for Safety-Critical Automotive Systems. ICCVE 2019: 1-6 - 2018
- [c19]Kuen-Long Lu, Yung-Yuan Chen, Li-Ren Huang:
FMEDA-Based Fault Injection and Data Analysis in Compliance with ISO-26262. DSN Workshops 2018: 275-278 - 2016
- [c18]Yung-Yuan Chen, Kuen-Long Leu:
An Effective Two-Level Redundancy Approach for FlexRay Network Systems. DSN Workshops 2016: 168-175 - 2015
- [c17]Hsiang Huang, Kuen-Long Leu, Yung-Yuan Chen:
An effective multiple-level fault-tolerant framework for FlexRay network systems. ICCVE 2015: 54-55 - [c16]Kuen-Long Leu, Hsiang Huang, Yung-Yuan Chen, Li-Ren Huang, Kung-Ming Ji:
An intelligent brake-by-wire system design and analysis in accordance with ISO-26262 functional safety standard. ICCVE 2015: 150-156 - 2012
- [c15]Kuen-Long Leu, Jwu-E Chen, Chin-Long Wey, Yung-Yuan Chen:
Generic Reliability Analysis for Safety-Critical FlexRay Drive-By-Wire Systems. ICCVE 2012: 216-221 - [c14]Yung-Yuan Chen, Chia-Ming Lyu:
ECU-level fault-tolerant framework for safety-critical FlexRay network systems. ICTC 2012: 553-558 - 2010
- [j6]Yung-Yuan Chen, Kuen-Long Leu:
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment. Microprocess. Microsystems 34(1): 49-61 (2010)
2000 – 2009
- 2009
- [c13]Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu:
SoC-level risk assessment using FMEA approach in system design with SystemC. SIES 2009: 82-89 - [c12]Kuen-Long Leu, Chin-Long Wey, Jwu-E Chen, Yung-Yuan Chen:
Robustness investigation of the FlexRay system. SIES 2009: 148-151 - 2008
- [c11]Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen:
An Online Control Flow Check for VLIW Processor. PRDC 2008: 256-264 - [c10]Kun-Chun Chang, Yi-Chinag Wang, Chung-Hsien Hsu, Kuen-Long Leu, Yung-Yuan Chen:
System-Bus Fault Injection Framework in SystemC Design Platform. SSIRI 2008: 211-212 - [c9]Yung-Yuan Chen, Shu-Hao Hsu, Kuen-Long Leu:
An Estimation Model of Vulnerability for Embedded Microprocessors. SSIRI 2008: 224-225 - 2006
- [c8]Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin:
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors. CDES 2006: 196-202 - [c7]Yung-Yuan Chen, Kuen-Long Leu, Chao-Sung Yeh:
Fault-Tolerant VLIW Processor Design and Error Coverage Analysis. EUC 2006: 754-765 - 2005
- [j5]Yung-Yuan Chen:
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring. IEEE Trans. Computers 54(10): 1298-1313 (2005) - 2004
- [c6]Yung-Yuan Chen, Kun-Feng Chen:
Incorporating Signature-Monitoring Technique in VLIW Processors. DFT 2004: 395-402 - 2003
- [c5]Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai:
An Integrated Fault-Tolerant Design Framework for VLIW Processors. DFT 2003: 555-562
1990 – 1999
- 1999
- [c4]Yung-Yuan Chen:
Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring. EDCC 1999: 437-454 - 1997
- [j4]Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng:
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. IEEE Trans. Computers 46(12): 1363-1371 (1997) - 1995
- [c3]Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen:
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. VLSI Design 1995: 349-354 - 1994
- [j3]Yung-Yuan Chen, Shambhu J. Upadhyaya:
Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy. IEEE Trans. Computers 43(6): 737-748 (1994) - [c2]Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou:
An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. EDCC 1994: 421-438 - 1993
- [j2]Yung-Yuan Chen, Shambhu J. Upadhyaya:
Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy. IEEE Trans. Computers 42(6): 713-723 (1993) - [j1]Yung-Yuan Chen, Shambhu J. Upadhyaya:
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy. IEEE Trans. Computers 42(9): 1136-1141 (1993) - 1990
- [c1]Yung-Yuan Chen, Shambhu J. Upadhyaya:
An analysis of a reconfigurable binary tree architecture based on multiple-level redundancy. FTCS 1990: 192-199
Coauthor Index
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