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Shinji Komori
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1990 – 1999
- 1997
- [j3]Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma:
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE J. Solid State Circuits 32(11): 1712-1720 (1997) - 1996
- [j2]Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31(11): 1645-1655 (1996) - [c3]Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. ITC 1996: 319-324 - 1991
- [c2]Toshiyuki Tamura, Shinji Komori, Fumiyasu Asai, Hirono Tsubota, Hisakazu Sato, Hidehiro Takata, Yoshihiro Seguchi, Takeshi Tokuda, Hiroaki Terada:
A Data-Driven Architecture for Distributed Parallel Processing. ICCD 1991: 218-224
1980 – 1989
- 1989
- [j1]Shinji Komori, Kenji Shima, Souichi Miyata, Toshiya Okamoto, Hiroaki Terada:
The data-driven microprocessor. IEEE Micro 9(3): 45-59 (1989) - 1987
- [c1]Katsuhiko Asada, Hiroaki Terada, Satoshi Matsumoto, Souichi Miyata, Hajime Asano, Hiroki Miura, Masahisa Shimizu, Shinji Komori, Takeshi Fukuhara, Kenji Shima:
Hardware Structure of a One-Chip Data Driven Processor: Q-p. ICPP 1987: 327-329
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