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ORCIDToshihiro Hattori
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2020 – today
- 2023
[j20]Toshihiro Hattori:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 490 (2023)- 2021
- [j19]Sheldon X.-D. Tan
, Toshihiro Hattori:
The 2021 Asia and South Pacific Design Automation Conference (ASPDAC). IEEE Des. Test 38(3): 121-122 (2021) - 2020
- [j18]Hiroyuki Kondo, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Noriaki Sakamoto, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Kosuke Yayama:
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D. IEEE J. Solid State Circuits 55(1): 133-144 (2020)
2010 – 2019
- 2019
- [c24]Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Tadaaki Yamauchi, Hiroyuki Kondo:
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D. ISSCC 2019: 54-56 - 2017
- [j17]Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2878-2887 (2017) - 2016
- [c23]Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. ISSCC 2016: 78-79 - 2015
- [j16]Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. IEEE J. Solid State Circuits 50(1): 92-101 (2015) - 2014
- [c22]Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. ISSCC 2014: 178-179 - 2013
- [j15]Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Takeshi Kataoka, Toshihiro Hattori:
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor. IEEE Micro 33(6): 26-36 (2013) - [c21]Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. ISSCC 2013: 156-157 - 2011
- [c20]Toshihiro Hattori:
Low-power and high-performance technologies for mobile SoC in LTE era. ISLPED 2011: 1-2 - 2010
- [j14]Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. IEEE J. Solid State Circuits 45(1): 59-68 (2010) - [j13]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010) - [c19]Shohei Iwata, Toshihiro Hattori, Motohiko Isaka:
On coding for nonbinary sources with side information at the decoder. ISITA 2010: 88-93
2000 – 2009
- 2009
- [j12]Naohiko Irie, Toshihiro Hattori:
Multi-Core/Multi-IP Technology for Embedded Applications. IEICE Trans. Electron. 92-C(10): 1232-1239 (2009) - [j11]Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama:
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. IEEE J. Solid State Circuits 44(1): 83-89 (2009) - [j10]Fumio Arakawa, Takashi Okada, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori:
An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU. Microprocess. Microsystems 33(4): 254-259 (2009) - [c18]Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka:
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. ASP-DAC 2009: 535-539 - [c17]Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342mW mobile application processor with full-HD multi-standard video codec. ISSCC 2009: 158-159 - [c16]Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2008
- [c15]Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller:
Multicore design is the challenge! what is the solution? DAC 2008: 128-130 - [c14]Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91 - [c13]Masao Naruse, Tatsuya Kamei, Toshihiro Hattori, Takahiro Irita, Kenichi Nitta, Takao Koike, Shinichi Yoshioka, Koji Ohno, Masahito Saigusa, Minoru Sakata, Yukio Kodama, Yuji Arai, Teruyoshi Komuro:
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. ISSCC 2008: 260-261 - 2007
- [j9]Andrew B. Kahng, Ira Chayut, John M. Cohn, Toshihiro Hattori, Jeong-Taek Kong, Pierre G. Paulin, Rich Tobias:
Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. IEEE Des. Test Comput. 24(1): 83-93 (2007) - [j8]Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu:
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Trans. Electron. 90-C(4): 657-665 (2007) - [j7]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. IEEE J. Solid State Circuits 42(1): 74-83 (2007) - [c12]Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara:
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. ISSCC 2007: 100-590 - [c11]Masayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral:
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. ISSCC 2007: 274-602 - 2006
- [j6]Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori:
Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. IEICE Trans. Electron. 89-C(3): 287-294 (2006) - [j5]Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Osamu Nishii, Toshihiro Hattori:
SH-X: An embedded processor core for consumer appliances. J. Embed. Comput. 2(1): 83-90 (2006) - [j4]Fumio Arakawa, Tetsuya Yamada, Takashi Okada, Makoto Ishikawa, Yuki Kondo, Motokazu Ozawa, Tomoyuki Kodama, Osamu Nishii, Toshihiro Hattori, Tatsuya Kamei, Junichi Nishimoto, Shinichi Yoshioka:
Development of processor cores for digital consumer appliances. Syst. Comput. Jpn. 37(3): 10-19 (2006) - [c10]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295 - [c9]Masayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka, Koji Ohno:
SH-MobileG1: A single-chip application and dual-mode baseband processor. Hot Chips Symposium 2006: 1-24 - [c8]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. ISSCC 2006: 2200-2209 - [c7]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. ISSCC 2006: 2210-2219 - 2005
- [j3]Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Motokazu Ozawa, Saneaki Tamaki, Mikio Furuyama, Tadashi Hoshi, Fumio Arakawa, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, Toshihiro Hattori:
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Trans. Electron. 88-C(4): 528-535 (2005) - [j2]Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori:
SH-X: an embedded processor core for consumer appliances. SIGARCH Comput. Archit. News 33(3): 33-40 (2005) - [c6]Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori:
Low-Power Design of 90-nm SuperH Processor Core. ICCD 2005: 258-266 - [c5]Shoichi Kamae, Takahiro Irita, Akifumi Tsukimori, Saneaki Tarnaki, Toshihiro Hattori, Shinichi Yoshioka:
SH-mobile - low power application processor for cellular [3G cellular phones]. ISCAS (5) 2005: 5349-5352 - 2004
- [c4]Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori:
SH-X: an embedded processor core for consumer appliances. MEDEA@PACT 2004: 33-40 - 2003
- [c3]Toshihiro Hattori:
Design methodology of low-power microprocessors. ASP-DAC 2003: 390-393 - 2001
- [c2]Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori:
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. ASP-DAC 2001: 267-268
1990 – 1999
- 1999
- [j1]Hiroyuki Mizuno, Koichiro Ishibashi, Takanori Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, Kunio Uchiyama:
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. IEEE J. Solid State Circuits 34(11): 1492-1500 (1999) - 1998
- [c1]Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura:
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. DAC 1998: 246-249
Coauthor Index
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