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ORCIDFrank Vahid
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- affiliation: University of California, Riverside, USA
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2020 – today
- 2024
[j56]Frank Vahid:
AI in CS Education: Opportunities, Challenges, and Pitfalls to Avoid. Inroads 15(3): 52-57 (2024)- [c147]Benjamin Denzler
, Frank Vahid, Ashley Pang, Mariam Salloum:
Style Anomalies Can Suggest Cheating in CS1 Programs. ITiCSE (1) 2024 - [c146]Ashley Pang, Frank Vahid:
ChatGPT and Cheat Detection in CS1 Using a Program Autograding System. ITiCSE (1) 2024 - [c145]Ashley Pang, Frank Vahid:
Performance Analysis and Interviews of Non-CS-Major Students Sanctioned for Cheating in CS1. ITiCSE (1) 2024 - [c144]Frank Vahid, Ashley Pang:
Experiences Teaching a CS1 Common Course across 7 Institutions. SIGCSE (1) 2024: 1354-1360 - [c143]Frank Vahid, Ashley Pang, Benjamin Denzler:
Towards Comprehensive Metrics for Programming Cheat Detection. SIGCSE (1) 2024: 1361-1367 - [c142]Frank Vahid:
CS1 Instructors: Flexibility in Content Approaches is Justified, and Can Enable More Cross-University Cooperation. SIGCSE (1) 2024: 1368-1373 - [c141]Benjamin Denzler, Frank Vahid, Ashley Pang:
Style Anomalies Can Suggest Cheating in CS1 Programs. SIGCSE (2) 2024: 1624-1625 - [c140]Colleen M. Lewis, Cynthia Bailey Lee, Adam Blank, Maria Camarena, Manuel Hernández, Frank Vahid:
Microteaching: Binary Heaps, Side-Channel Attacks, Equitable Grading, Java Classes, Loops, and 3D Java. SIGCSE (2) 2024: 1869-1870 - 2023
- [j55]Chelsea Gordon, Roman Lysecky, Frank Vahid:
Less Is More: Students Skim Lengthy Online Textbooks. IEEE Trans. Educ. 66(2): 123-129 (2023) - [c139]Ashley Pang, Frank Vahid:
Variability-Inducing Requirements for Programs: Increasing Solution Variability for Similarity Checking. ITiCSE (1) 2023: 430-435 - [c138]Frank Vahid, Ashley Pang, Kelly Downey:
Towards Grading for Equity in a Large CS1 Class: An Experience with Flexible Deadlines and Resubmissions. ITiCSE (2) 2023: 646 - [c137]Frank Vahid, Ashley Pang, Kelly Downey:
Impact of Student Time Spent on Performance in a CS1 Class, Including Prior Experience Effect. ITiCSE (2) 2023: 664 - [c136]Frank Vahid, Kelly Downey, Lizbeth Areizaga, Ashley Pang:
Experiences Teaching Coral Before C++ in CS1. SIGCSE (1) 2023: 340-345 - [c135]Frank Vahid, Kelly Downey, Ashley Pang, Chelsea Gordon:
Impact of Several Low-Effort Cheating-Reduction Methods in a CS1 Class. SIGCSE (1) 2023: 486-492 - [c134]Chelsea Gordon, Stanley Zhao, Frank Vahid:
Ultra-Lightweight Early Prediction of At-Risk Students in CS1. SIGCSE (1) 2023: 764-770 - [c133]Peter Brusilovsky, Barbara J. Ericson, Cay S. Horstmann, Christian Servin, Frank Vahid, Craig B. Zilles:
Significant Trends in CS Educational Material: Current and Future. SIGCSE (2) 2023: 1253 - 2022
- [j54]Jeffrey Miller, Charles Wallace, Frank Vahid:
Member spotlight. ACM SIGCSE Bull. 54(1): 8-9 (2022) - 2021
- [c132]Chelsea Gordon, Roman Lysecky, Frank Vahid:
The shift from static college textbooks to customizable content: A case study at zyBooks. FIE 2021: 1-7 - [c131]Joe Michael Allen, Frank Vahid:
Concise Graphical Representations of Student Effort on Weekly Many Small Programs. SIGCSE 2021: 349-354
2010 – 2019
- 2019
- [j53]Maral Amir, Frank Vahid, Tony Givargis:
Switching Predictive Control Using Reconfigurable State-Based Model. ACM Trans. Design Autom. Electr. Syst. 24(1): 2:1-2:21 (2019) - [c130]Frank Vahid, Alex D. Edgcomb, Roman Lysecky, Yamuna Rajasekhar:
New web-based learning content for core programming concepts using Coral. FIE 2019: 1-5 - [c129]Joe Michael Allen, Frank Vahid, Alex D. Edgcomb, Kelly Downey, Kris Miller:
An Analysis of Using Many Small Programs in CS1. SIGCSE 2019: 585-591 - [c128]Frank Vahid, Roman Lysecky:
Auto-Graded Programming Labs: Dos and Don'ts for Less-Stressed Higher-Performing Students, Reduced Grading Time, and Happier Teachers, . SIGCSE 2019: 1250 - 2018
- [c127]Nabeel Alzahrani, Frank Vahid, Alex D. Edgcomb, Kevin Nguyen, Roman Lysecky:
Python Versus C++: An Analysis of Student Struggle on Small Coding Exercises in Introductory Programming Courses. SIGCSE 2018: 86-91 - [c126]Alex D. Edgcomb, Frank Vahid:
Interactive, Language-neutral Flowcharts and Pseudocode for Teaching Core CS0/1 Programming Concepts: (Abstract Only). SIGCSE 2018: 1102 - [c125]Roman Lysecky, Frank Vahid:
Teaching Students a Systematic Approach to Debugging: (Abstract Only). SIGCSE 2018: 1104 - 2017
- [c124]Alex D. Edgcomb, Frank Vahid, Roman Lysecky, Susan Lysecky:
Getting Students to Earnestly Do Reading, Studying, and Homework in an Introductory Programming Class. SIGCSE 2017: 171-176 - 2015
- [j52]Bailey Miller, Frank Vahid, Tony Givargis, Philip Brisk:
Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation. ACM Trans. Reconfigurable Technol. Syst. 7(4): 37:1-37:22 (2015) - [c123]Alex D. Edgcomb, Frank Vahid:
How many points should be awarded for interactive textbook reading assignments? FIE 2015: 1-4 - [c122]Alex D. Edgcomb, Frank Vahid, Roman L. Lysecky:
Students learn more with less text that covers the same core topics. FIE 2015: 1-5 - [c121]Cay S. Horstmann, Smita Bakshi, Amruth Kumar, Frank Vahid:
Interactive Ebooks and Course Materials: A BOF for Authors and Instructors (Abstract Only). SIGCSE 2015: 695 - 2014
- [j51]Volkan Gunes, Steffen Peter, Tony Givargis, Frank Vahid:
A Survey on Concepts, Applications, and Challenges in Cyber-Physical Systems. KSII Trans. Internet Inf. Syst. 8(12): 4242-4268 (2014) - 2013
- [j50]Chen Huang, Frank Vahid, Tony Givargis:
Automatic synthesis of physical system differential equation models to a custom network of general processing elements on FPGAs. ACM Trans. Embed. Comput. Syst. 13(2): 23:1-23:27 (2013) - [j49]Alex D. Edgcomb, Frank Vahid:
Accurate and Efficient Algorithms that Adapt to Privacy-Enhanced Video for Improved Assistive Monitoring. ACM Trans. Manag. Inf. Syst. 4(3): 14:1-14:16 (2013) - [j48]Chen Huang, Bailey Miller, Frank Vahid, Tony Givargis:
Synthesis of networks of custom processing elements for real-time physical system emulation. ACM Trans. Design Autom. Electr. Syst. 18(2): 21:1-21:21 (2013) - [c120]Ting-Shuo Chou, Tony Givargis, Chen Huang, Bailey Miller, Frank Vahid:
An efficient compression scheme for checkpointing of FPGA-based digital mockups. ASP-DAC 2013: 632-637 - [c119]Bailey Miller, Frank Vahid, Tony Givargis:
Exploration with upgradeable models using statistical methods for physical model emulation. DAC 2013: 154:1-154:6 - [c118]Diane T. Rover, Yacob Astatke, Smita Bakshi, Frank Vahid:
An online revolution in learning and teaching. FIE 2013: 14 - [c117]Bailey Miller, Frank Vahid, Tony Givargis:
Embedding-based placement of processing element networks on FPGAs for physical model simulation. FPGA 2013: 181-190 - [c116]Alex D. Edgcomb, Frank Vahid:
Estimating Daily Energy Expenditure from Video for Assistive Monitoring. ICHI 2013: 184-191 - [c115]Alex D. Edgcomb, Frank Vahid:
Automated In-Home Assistive Monitoring with Privacy-Enhanced Video. ICHI 2013: 192-198 - 2012
- [j47]Alex D. Edgcomb, Frank Vahid:
Privacy perception and fall detection accuracy for in-home video assistive monitoring with privacy enhancements. SIGHIT Rec. 2(2): 6-15 (2012) - [j46]Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt:
Combining code reordering and cache configuration. ACM Trans. Embed. Comput. Syst. 11(4): 88:1-88:20 (2012) - [c114]Chen Huang, Bailey Miller, Frank Vahid, Tony Givargis:
Synthesis of custom networks of heterogeneous processing elements for complex physical system emulation. CODES+ISSS 2012: 215-224 - [c113]Bailey Miller, Frank Vahid, Tony Givargis:
MEDS: Mockup Electronic Data Sheets for automated testing of cyber-physical systems using digital mockups. DATE 2012: 1417-1420 - [c112]Alex D. Edgcomb, Frank Vahid:
Automated fall detection on privacy-enhanced video. EMBC 2012: 252-255 - [c111]Bailey Miller, Frank Vahid, Tony Givargis:
RIOS: a lightweight task scheduler for embedded systems. WESE 2012: 9 - [c110]Alex D. Edgcomb, Frank Vahid:
MNFL: the monitoring and notification flow language for assistive monitoring. IHI 2012: 191-200 - [c109]Bailey Miller, Frank Vahid, Tony Givargis:
Digital mockups for the testing of a medical ventilator. IHI 2012: 859-862 - 2011
- [j45]Chen Huang, Frank Vahid, Tony Givargis:
A Custom FPGA Processor for Physical Model Ordinary Differential Equation Solving. IEEE Embed. Syst. Lett. 3(4): 113-116 (2011) - [j44]Greg Stitt, Frank Vahid:
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators. ACM Trans. Design Autom. Electr. Syst. 16(3): 32:1-32:21 (2011) - [c108]Chen Huang, Frank Vahid:
Scalable object detection accelerators on FPGAs using custom design space exploration. SASP 2011: 115-121 - [c107]Alex D. Edgcomb, Frank Vahid:
Feature extractors for integration of cameras and sensors during end-user programming of assistive monitoring systems. Wireless Health 2011: 13 - 2010
- [c106]Scott Sirowy, Chen Huang, Frank Vahid:
Online SystemC emulation acceleration. DAC 2010: 30-35 - [c105]Chen Huang, Frank Vahid:
Server-side coprocessor updating for mobile devices with FPGAs. FPGA 2010: 125-134
2000 – 2009
- 2009
- [j43]Scott Sirowy, David Sheldon, Tony Givargis, Frank Vahid:
Virtual microcontrollers. SIGBED Rev. 6(1): 6 (2009) - [j42]Scott Sirowy, Chen Huang, Frank Vahid:
Dynamic acceleration management for SystemC emulation. SIGBED Rev. 6(3): 3 (2009) - [j41]Roman L. Lysecky, Frank Vahid:
Design and implementation of a MicroBlaze-based warp processor. ACM Trans. Embed. Comput. Syst. 8(3): 22:1-22:22 (2009) - [j40]Susan Lysecky, Frank Vahid:
Enabling nonexpert construction of basic sensor-based systems. ACM Trans. Comput. Hum. Interact. 16(1): 1:1-1:28 (2009) - [j39]Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt:
Fast Configurable-Cache Tuning With a Unified Second-Level Cache. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 80-91 (2009) - [c104]Scott Sirowy, Bailey Miller, Frank Vahid:
Portable SystemC-on-a-chip. CODES+ISSS 2009: 21-30 - [c103]Chen Huang, Frank Vahid:
Transmuting coprocessors: dynamic loading of FPGA coprocessors. DAC 2009: 848-851 - [c102]David Sheldon, Frank Vahid:
Making good points: application-specific pareto-point generation for design space exploration using statistical methods. FPGA 2009: 123-132 - 2008
- [j38]Frank Vahid, Greg Stitt, Roman L. Lysecky:
Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. Computer 41(7): 40-46 (2008) - [c101]Chen Huang, Frank Vahid:
Dynamic coprocessor management for FPGA-enhanced compute platforms. CASES 2008: 71-78 - [c100]Chen Huang, David Sheldon, Frank Vahid:
Dynamic tuning of configurable architectures: the AWW online algorithm. CODES+ISSS 2008: 97-102 - [c99]David Sheldon, Frank Vahid:
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. CODES+ISSS 2008: 155-160 - [c98]Frank Vahid, Tony Givargis:
Highly-cited ideas in system codesign and synthesis. CODES+ISSS 2008: 191-196 - [c97]Scott Sirowy, Greg Stitt, Frank Vahid:
C is for circuits: capturing FPGA circuits as sequential code for portability. FPGA 2008: 117-126 - [c96]David Sheldon, Frank Vahid:
A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design. FPGA 2008: 264 - [c95]Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid:
A table-based method for single-pass cache optimization. ACM Great Lakes Symposium on VLSI 2008: 71-76 - 2007
- [j37]Frank Vahid:
It's Time to Stop Calling Circuits "Hardware". Computer 40(9): 106-108 (2007) - [j36]Greg Stitt, Frank Vahid:
Binary synthesis. ACM Trans. Design Autom. Electr. Syst. 12(3): 34:1-34:30 (2007) - [c94]Greg Stitt, Frank Vahid:
Thread warping: a framework for dynamic synthesis of thread accelerators. CODES+ISSS 2007: 93-98 - [c93]Ann Gordon-Ross, Frank Vahid:
A Self-Tuning Configurable Cache. DAC 2007: 234-237 - [c92]Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid:
Two-level microprocessor-accelerator partitioning. DATE 2007: 313-318 - [c91]Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid:
Clock-frequency assignment for multiple clock domain systems-on-a-chip. DATE 2007: 397-402 - [c90]Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros:
A one-shot configurable-cache tuner for improved energy and performance. DATE 2007: 755-760 - [c89]David Sheldon, Frank Vahid, Stefano Lonardi:
Interactive presentation: Soft-core processor customization using the design of experiments paradigm. DATE 2007: 821-826 - [c88]Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid:
Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. FPL 2007: 533-536 - [c87]Scott Sirowy, Frank Vahid:
Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning. IESS 2007: 145-154 - [i3]Greg Stitt, Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. CoRR abs/0710.4700 (2007) - [i2]Roman L. Lysecky, Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. CoRR abs/0710.4705 (2007) - [i1]Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid:
System Synthesis for Networks of Programmable Blocks. CoRR abs/0710.4798 (2007) - 2006
- [j35]Roman L. Lysecky, Greg Stitt, Frank Vahid:
Warp Processors. ACM Trans. Design Autom. Electr. Syst. 11(3): 659-681 (2006) - [c86]Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid:
Configurable cache subsetting for fast cache tuning. DAC 2006: 695-700 - [c85]Susan Lysecky, Frank Vahid:
Automated Generation of Basic Custom Sensor-Based Embedded Computing Systems Guided by End-User Optimization Criteria. UbiComp 2006: 69-86 - [c84]Susan Lysecky, Frank Vahid:
Automated Application-Specific Tuning of Parameterized Sensor-Based Embedded System Building Blocks. UbiComp 2006: 507-524 - [c83]David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen:
Application-specific customization of parameterized FPGA soft-core processors. ICCAD 2006: 261-268 - [c82]David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky:
Conjoining soft-core FPGA processors. ICCAD 2006: 694-701 - [c81]Greg Stitt, Frank Vahid, Walid A. Najjar:
A code refinement methodology for performance-improved synthesis from C. ICCAD 2006: 716-723 - 2005
- [j34]Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar:
A way-halting cache for low-energy high-performance systems. ACM Trans. Archit. Code Optim. 2(1): 34-54 (2005) - [j33]Ann Gordon-Ross, Frank Vahid:
Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware. IEEE Trans. Computers 54(10): 1203-1215 (2005) - [j32]Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
A highly configurable cache for low energy embedded systems. ACM Trans. Embed. Comput. Syst. 4(2): 363-387 (2005) - [c80]Susan Cotterell, Frank Vahid:
A logic block enabling logic configuration by non-experts in sensor networks. CHI Extended Abstracts 2005: 1925-1928 - [c79]Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth:
Hardware/software partitioning of software binaries: a case study of H.264 decode. CODES+ISSS 2005: 285-290 - [c78]Roman L. Lysecky, Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. DATE 2005: 18-23 - [c77]Greg Stitt, Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. DATE 2005: 396-397 - [c76]Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid:
System Synthesis for Networks of Programmable Blocks. DATE 2005: 888-893 - [c75]Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan:
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. FCCM 2005: 57-62 - [c74]Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid:
Techniques for synthesizing binaries to an advanced register/memory structure. FPGA 2005: 118-124 - [c73]Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers:
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). FPGA 2005: 271 - [c72]Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt:
A first look at the interplay of code reordering and configurable caches. ACM Great Lakes Symposium on VLSI 2005: 416-421 - [c71]Greg Stiff, Frank Vahid:
New decompilation techniques for binary-level co-processor generation. ICCAD 2005: 547-554 - [c70]Susan Cotterell, Ryan Mannion, Frank Vahid, Harry Hsieh:
eBlocks - an enabling technology for basic sensor based systems. IPSN 2005: 422-427 - [c69]Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt:
Fast configurable-cache tuning with a unified second-level cache. ISLPED 2005: 323-326 - 2004
- [j31]Greg Stitt, Frank Vahid, Shawn Nematbakhsh:
Energy savings and speedups from partitioning critical software loops to hardware in embedded systems. ACM Trans. Embed. Comput. Syst. 3(1): 218-232 (2004) - [j30]Chuanjun Zhang, Frank Vahid, Roman L. Lysecky:
A self-tuning cache architecture for embedded systems. ACM Trans. Embed. Comput. Syst. 3(2): 407-425 (2004) - [j29]Roman L. Lysecky, Susan Cotterell, Frank Vahid:
A fast on-chip profiler memory using a pipelined binary tree. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 120-122 (2004) - [c68]Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan:
Dynamic FPGA routing for just-in-time FPGA compilation. DAC 2004: 954-959 - [c67]Chuanjun Zhang, Frank Vahid, Roman L. Lysecky:
A Self-Tuning Cache Architecture for Embedded Systems. DATE 2004: 142-147 - [c66]Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt:
Automatic Tuning of Two-Level Caches to Embedded Applications. DATE 2004: 208-213 - [c65]Chuanjun Zhang, Jun Yang, Frank Vahid:
Low Static-Power Frequent-Value Data Caches. DATE 2004: 214-219 - [c64]Chuanjun Zhang, Frank Vahid:
Using a Victim Buffer in an Application-Specific Memory Hierarchy. DATE 2004: 220-227 - [c63]Roman L. Lysecky, Frank Vahid:
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. DATE 2004: 480-485 - [c62]Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers:
A quantitative analysis of the speedup factors of FPGAs over processors. FPGA 2004: 162-170 - [c61]Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar:
A way-halting cache for low-energy high-performance systems. ISLPED 2004: 126-131 - [c60]Susan Cotterell, Kelly Downey, Frank Vahid:
Applications and experiments with eBlocks - electronic blocks for basic sensor-based systems. SECON 2004: 7-15 - [p1]Ann Gordon-Ross, Chuanjun Zhang, Frank Vahid, Nikil D. Dutt:
Tuning Caches to Applications for Low-Energy Embedded Systems. Ultra Low-Power Electronics and Design 2004: 103-122 - 2003
- [j28]Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar:
A Way-Halting Cache for Low-Energy High-Performance Systems. IEEE Comput. Archit. Lett. 2 (2003) - [j27]Frank Vahid:
The Softening of Hardware. Computer 36(4): 27-34 (2003) - [j26]Frank Vahid:
Making the Best of Those Extra Transistors. IEEE Des. Test Comput. 20(1): 96- (2003) - [j25]Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt:
Highly configurable platforms for embedded computing systems. Microelectron. J. 34(11): 1025-1029 (2003) - [j24]Ann Gordon-Ross, Susan Cotterell, Frank Vahid:
Tiny instruction caches for low power embedded systems. ACM Trans. Embed. Comput. Syst. 2(4): 449-481 (2003) - [c59]Ann Gordon-Ross, Frank Vahid:
Frequent loop detection using efficient non-intrusive on-chip hardware. CASES 2003: 117-124 - [c58]Roman L. Lysecky, Frank Vahid:
A codesigned on-chip logic minimizer. CODES+ISSS 2003: 109-113 - [c57]Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh:
First results with eBlocks: embedded systems building blocks. CODES+ISSS 2003: 168-175 - [c56]Greg Stitt, Roman L. Lysecky, Frank Vahid:
Dynamic hardware/software partitioning: a first approach. DAC 2003: 250-255 - [c55]Roman L. Lysecky, Frank Vahid:
On-chip logic minimization. DAC 2003: 334-337 - [c54]Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
A Highly-Configurable Cache Architecture for Embedded Systems. ISCA 2003: 136-146 - [c53]Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
Energy Benefits of a Configurable Line Size Cache for Embedded Systems. ISVLSI 2003: 87-91 - [c52]Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt:
Profiling tools for hardware/software partitioning of embedded applications. LCTES 2003: 189-198 - [c51]Frank Vahid:
Embedded System Design: UCR's Undergraduate Three-Course Sequence. MSE 2003: 72-73 - [c50]Chuanjun Zhang, Frank Vahid:
Cache Configuration Exploration on Prototyping Platforms. IEEE International Workshop on Rapid System Prototyping 2003: 164- - 2002
- [b1]Frank Vahid, Tony Givargis:
Embedded system design - a unified hardware / software introduction. Wiley-VCH 2002, ISBN 978-0-471-45303-1, pp. I-XXI, 1-324 - [j23]Ann Gordon-Ross, Susan Cotterell, Frank Vahid:
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. IEEE Comput. Archit. Lett. 1 (2002) - [j22]Tony Givargis, Frank Vahid:
Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms. Des. Autom. Embed. Syst. 7(1-2): 35-51 (2002) - [j21]Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar:
Improving Software Performance with Configurable Logic. Des. Autom. Embed. Syst. 7(4): 325-339 (2002) - [j20]Greg Stitt, Frank Vahid:
Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. IEEE Des. Test Comput. 19(6): 36-43 (2002) - [j19]Frank Vahid, Tony Givargis, Susan Cotterell:
Power Estimator Development for Embedded System Memory Tuning. J. Circuits Syst. Comput. 11(5): 459-476 (2002) - [j18]Tony Givargis, Frank Vahid:
Platune: a tuning framework for system-on-a-chip platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1317-1327 (2002) - [j17]Roman L. Lysecky, Frank Vahid:
Prefetching for improved bus wrapper performance in cores. ACM Trans. Design Autom. Electr. Syst. 7(1): 58-90 (2002) - [j16]Frank Vahid:
Partitioning sequential programs for CAD using a three-step approach. ACM Trans. Design Autom. Electr. Syst. 7(3): 413-429 (2002) - [j15]Tony Givargis, Frank Vahid, Jörg Henkel:
System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 416-422 (2002) - [j14]Tony Givargis, Frank Vahid, Jörg Henkel:
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 856-863 (2002) - [c49]Brian Grattan, Greg Stitt, Frank Vahid:
Codesign-extended applications. CODES 2002: 1-6 - [c48]Roman L. Lysecky, Susan Cotterell, Frank Vahid:
A fast on-chip profiler memory. DAC 2002: 28-33 - [c47]Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid:
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. FCCM 2002: 143-151 - [c46]Greg Stitt, Frank Vahid:
Hardware/software partitioning of software binaries. ICCAD 2002: 164-170 - [c45]Susan Cotterell, Frank Vahid:
Synthesis of customized loop caches for core-based embedded systems. ICCAD 2002: 655-662 - [c44]Ann Gordon-Ross, Frank Vahid:
Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach. ICCD 2002: 446-449 - [c43]Chuanjun Zhang, Frank Vahid:
A power-configurable bus for embedded systems. ISCAS (5) 2002: 809-812 - [c42]Frank Vahid, Susan Cotterell:
Tuning of Loop Cache Architectures to Programs in Embedded System Design. ISSS 2002: 8-13 - 2001
- [j13]Frank Vahid, Tony Givargis:
Platform Tuning for Embedded Systems Design. Computer 34(3): 112-114 (2001) - [j12]Frank Vahid, Rilesh Patel, Greg Stitt:
Propagating constants past software to hardware peripherals in fixed-application embedded systems. SIGARCH Comput. Archit. News 29(5): 25-30 (2001) - [j11]Tony Givargis, Frank Vahid, Jörg Henkel:
Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs. IEEE Trans. Very Large Scale Integr. Syst. 9(4): 500-508 (2001) - [c41]Tony Givargis, Frank Vahid, Jörg Henkel:
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores. ASP-DAC 2001: 306-312 - [c40]Tony Givargis, Frank Vahid, Jörg Henkel:
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip. ICCAD 2001: 25-30 - [c39]Frank Vahid, Ann Gordon-Ross:
A self-optimizing embedded microprocessor using a loop table for low power. ISLPED 2001: 219-224 - 2000
- [c38]Tony Givargis, Frank Vahid, Jörg Henkel:
A hybrid approach for core-based system-level power modeling. ASP-DAC 2000: 141-146 - [c37]Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky:
A first-step towards an architecture tuning methodology for low power. CASES 2000: 187-192 - [c36]Tony Givargis, Frank Vahid:
Parameterized system design. CODES 2000: 98-102 - [c35]Roman L. Lysecky, Frank Vahid, Tony Givargis:
Techniques for Reducing Read Latency of Core Bus Wrappers. DATE 2000: 84-91 - [c34]Jörg Henkel, Tony Givargis, Frank Vahid:
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. DATE 2000: 333-338 - [c33]Tony Givargis, Frank Vahid, Jörg Henkel:
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores. ISSS 2000: 163-171 - [c32]Roman L. Lysecky, Frank Vahid, Tony Givargis:
Experiments with the Peripheral Virtual Component Interface. ISSS 2000: 221-224 - [e3]Frank Vahid, Jan Madsen:
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000. ACM 2000, ISBN 1-58113-268-9 [contents]
1990 – 1999
- 1999
- [j10]Frank Vahid:
Techniques for minimizing and balancing I/O during functional partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(1): 69-75 (1999) - [j9]Frank Vahid:
Procedure cloning: a transformation for improved system-level functional partitioning. ACM Trans. Design Autom. Electr. Syst. 4(1): 70-96 (1999) - [c31]Frank Vahid, Tony Givargis:
The case for a configure-and-execute paradigm. CODES 1999: 59-63 - [c30]Enoch Hwang, Frank Vahid, Yu-Chin Hsu:
FSMD Functional Partitioning for Low Power. DATE 1999: 22-27 - [c29]Tony Givargis, Jörg Henkel, Frank Vahid:
Interface and cache power exploration for core-based embedded system design. ICCAD 1999: 270-273 - [c28]Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis:
Pre-Fetching for Improved Core Interfacing. ISSS 1999: 51-55 - [e2]Ahmed Amine Jerraya, Luciano Lavagno, Frank Vahid:
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999. ACM 1999, ISBN 1-58113-132-1 [contents] - 1998
- [j8]Frank Vahid, Thuy Dm Le, Yu-Chin Hsu:
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. ACM Trans. Design Autom. Electr. Syst. 3(2): 181-208 (1998) - [j7]Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 84-100 (1998) - [c27]Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
System-level exploration with SpecSyn. DAC 1998: 812-817 - [c26]Frank Vahid, Tony Givargis:
Incorporating Cores into System-Level Specification. ISSS 1998: 43-50 - [c25]Tony Givargis, Frank Vahid:
Interface Exploration for Reduced Power in Core-Based Systems. ISSS 1998: 117-124 - [c24]Frank Vahid:
A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes. ISSS 1998: 152-157 - 1997
- [j6]Frank Vahid, Thuy Dm Le:
Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning. Des. Autom. Embed. Syst. 2(2): 237-261 (1997) - [c23]Frank Vahid:
Modifying Min-Cut for Hardware and Software Functional Partitioning. CODES 1997: 43-48 - [c22]Frank Vahid, Linus Tauro:
An Object-Oriented Communication Library for Hardware-Software CoDesign. CODES 1997: 81-86 - [c21]Frank Vahid:
Procedure cloning: a transformation for improved system-level functional partitioning. ED&TC 1997: 487-492 - [c20]Frank Vahid:
I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning. FPGA 1997: 27-34 - [c19]Frank Vahid:
Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning. ISSS 1997: 107-112 - [e1]Frank Vahid, Francky Catthoor:
Proceedings of the 10th International Symposium on System Synthesis, ISSS '97, Antwerp, Belgium, September 17-19, 1997. ACM / IEEE Computer Society 1997, ISBN 0-8186-7949-2 [contents] - 1996
- [j5]Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung:
System design methodologies: aiming at the 100 h design cycle. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 70-82 (1996) - [c18]Frank Vahid, Thuy Dm Le:
Towards a Model for Hardware and Software Functional Partitioning. CODES 1996: 116-123 - [c17]Frank Vahid, Thuy Dm Le, Yu-Chin Hsu:
A Comparison of Functional and Structural Partitioning. ISSS 1996: 121-126 - 1995
- [j4]Daniel D. Gajski, Frank Vahid:
Specification and Design of Embedded Hardware-Software Systems. IEEE Des. Test Comput. 12(1): 53-67 (1995) - [j3]Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 694-706 (1995) - [j2]Frank Vahid, Daniel D. Gajski:
Incremental hardware estimation during hardware/software functional partitioning. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 459-464 (1995) - [c16]Frank Vahid, Daniel D. Gajski:
SLIF: a specification-level intermediate format for system design. ED&TC 1995: 185-189 - [c15]Frank Vahid, Daniel D. Gajski:
Closeness metrics for system-level functional partitioning. EURO-DAC 1995: 328-333 - [c14]Frank Vahid:
Procedure exlining: a new system-level specification transformation. EURO-DAC 1995: 508-513 - [c13]Frank Vahid, Daniel D. Gajski:
Clustering for improved system-level functional partitioning. ISSS 1995: 28-35 - [c12]Frank Vahid:
Procedure exlining: a transformation for improved system and behavioral synthesis. ISSS 1995: 84-89 - 1994
- [c11]Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung:
100-hour design cycle: a test case. EURO-DAC 1994: 144-149 - [c10]Frank Vahid, Daniel D. Gajski, Jie Gong:
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. EURO-DAC 1994: 214-219 - [c9]Daniel Gajski, Frank Vahid, Sanjiv Narayan:
A System-Design Methodology: Executable-Specification Refinement. EDAC-ETC-EUROASIC 1994: 458-463 - [c8]Frank Vahid, Daniel D. Gajski, Sanjiv Narayan:
A transformation for integrating VHDL behavioral specification with synthesis and software generation. EURO-DAC 1994: 552-557 - 1993
- [c7]Loganath Ramachandran, Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
Synthesis of functions and procedures in behavioral VHDL. EURO-DAC 1993: 560-565 - 1992
- [j1]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
System Specification with the SpecCharts Language. IEEE Des. Test Comput. 9(4): 6-13 (1992) - [c6]Frank Vahid, Daniel Gajski:
Specification Partitioning for System Design. DAC 1992: 219-224 - [c5]Loganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
Semantics and synthesis of signals in behavioral VHDL. EURO-DAC 1992: 616-621 - [c4]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
System Level Specification and Synthesis. VLSI Design 1992: 103-108 - 1991
- [c3]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
Translating system specifications to VHDL. EURO-DAC 1991: 390-394 - [c2]Sanjiv Narayan, Frank Vahid, Daniel Gajski:
System Specification and Synthesis with the SpecCharts Language. ICCAD 1991: 266-269 - [c1]Frank Vahid, Daniel Gajski:
Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation. ICCAD 1991: 362-365
Coauthor Index
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