"Applying TMR in Hardware Accelerators Generated by High-Level Synthesis ..."

André Flores dos Santos et al. (2017)

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DOI: 10.1007/978-3-319-56258-2_18

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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André Flores dos Santos, Lucas Antunes Tambara, Fabio Benevenuti, Jorge L. Tonfat, Fernanda Lima Kastensmidt:
Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. ARC 2017: 202-213

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