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"A Parallel Pipelined SAT Solver for FPGAs."

Mark Redekopp, Andreas Dandalis (2000)

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DOI: 10.1007/3-540-44614-1_50

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-10

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  - conf/fpl/RedekoppD00
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Mark Redekopp, Andreas Dandalis:
A Parallel Pipelined SAT Solver for FPGAs. FPL 2000: 462-468

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