"Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 ..."

Yervant Zorian, Najmi Jarwala (1989)

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DOI: 10.1109/ICCD.1989.63432

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-28

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Yervant Zorian, Najmi Jarwala:
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. ICCD 1989: 580-584

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