"Test-pattern Generation for VLSI Circuits in a Prolog Environment."

Rajiv Gupta (1986)

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DOI: 10.1007/3-540-16492-8_100

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-23

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Rajiv Gupta:
Test-pattern Generation for VLSI Circuits in a Prolog Environment. ICLP 1986: 528-535

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