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"1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered ..."

Yisuo Li et al. (2021)

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DOI: 10.1109/IMW51353.2021.9439625

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-19

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  dblp key:
  - conf/imw2/LiKISSBRKSHM21
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  - https://dblp.org/rec/conf/imw2/LiKISSBRKSHM21
Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka:
1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. IMW 2021: 1-4

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