"32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time ..."

Wanghua Wu et al. (2021)

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DOI: 10.1109/ISSCC42613.2021.9365850

access: closed

type: Conference or Workshop Paper

metadata version: 2021-03-10

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Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho:
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. ISSCC 2021: 444-446

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