"Novel Cell Architectures with Back-side Transistor Contacts for Scaling ..."

Mauro J. Kobrinsky et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185319

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type: Conference or Workshop Paper

metadata version: 2023-08-31

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Mauro J. Kobrinsky, J. D. Silva, E. Mannebach, S. Mills, M. Abd El Qader, O. Adebayo, N. Arkali Radhakrishna, M. Beasley, J. Chawla, S. Chugh, A. Dasgupta, U. Desai, E. De Re, G. Dewey, T. Edwards, C. Engel, V. Gudmundsson, Jeffery Hicks, B. Krist, R. Mehandru, Inanc Meric, Patrick Morrow, D. Nandi, P. Patel, R. Ramamurthy, D. Samanta, L. Shoer, A. St Amour, L. H. Tan, Sukru Yemenicioglu, X. Wang, T. Ghani:
Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance. VLSI Technology and Circuits 2023: 1-2

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