"A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with ..."

Masanori Shirahama et al. (2005)

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DOI: 10.1109/JSSC.2005.845995

access: closed

type: Journal Article

metadata version: 2024-02-05

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Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi:
A 400-MHz random-cycle dual-port interleaved DRAM (D²RAM) with standard CMOS Process. IEEE J. Solid State Circuits 40(5): 1200-1207 (2005)

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