"Ultra-Thinning of C4 Integrated Circuits for Backside Analysis during ..."

Ted R. Lundquist et al. (2001)

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DOI: 10.1016/S0026-2714(01)00171-8

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type: Journal Article

metadata version: 2020-02-22

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Ted R. Lundquist, E. Delenia, J. Harroun, E. LeRoy, Chun-Cheng Tsao:
Ultra-Thinning of C4 Integrated Circuits for Backside Analysis during First Silicon Debug. Microelectron. Reliab. 41(9-10): 1545-1549 (2001)

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