"High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs."

Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna (2007)

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DOI: 10.1109/TPDS.2007.1068

access: closed

type: Journal Article

metadata version: 2020-10-02

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  - https://dblp.org/rec/journals/tpds/ZhuoMP07
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna:
High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE Trans. Parallel Distributed Syst. 18(10): 1377-1392 (2007)

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