"A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator ..."

Jun-Sheng Ng et al. (2022)

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DOI: 10.1109/TVLSI.2022.3175180

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type: Journal Article

metadata version: 2023-08-28

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Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, Bah-Hwee Gwee:
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1144-1157 (2022)

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