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ORCIDA-SSCC 2017: Seoul, Korea (South)
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. IEEE 2017, ISBN 978-1-5386-3178-2
- Brendan Farley, Christophe Erdmann, Bruno Vaz, John McGrath, Edward Cullen, Bob Verbruggen, Roberto Pelliconi, Daire Breathnach, Peng Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, David Melinn, Kwee Peng Yap, Liam Madden:
A programmable RFSoC in 16nm FinFET technology for wideband communications. 1-4 - Jongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee, In-Young Lee, Byungki Han, Seunghyun Oh, Thomas Byunghak Cho:
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS. 5-8 - Chia-Fu Lee, Hon-Jarn Lin, Chiu-Wang Lien, Yu-Der Chih, Tsung-Yung Jonathan Chang:
A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application. 9-12 - Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii:
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode. 13-16 - Mahesh K. Kumashikar, Shridhar G. Bendi, Srikanth Nimmagadda, Anup Jyoti Deka, Anil Agarwal:
14nm Broadwell Xeon® processor family: Design methodologies and optimizations. 17-20 - Zhichao Tan, Khiem Nguyen, Jeff Yan, Howard Samuels, Shane Keating, Paul Crocker, Bill Clark:
A dual-axis MEMS vibratory gyroscope ASIC with 0.0061°/s/VHz noise floor over 480 Hz bandwidth. 21-24 - Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
:
Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. 25-28 - Yuxuan Luo, Kok-Hin Teng, Yongfu Li, Wei Mao, Chun-Huat Heng, Yong Lian:
A 93μW 11Mbps wireless vital signs monitoring SoC with 3-lead ECG, bio-impedance, and body temperature. 29-32 - Tao Tang, Wang Ling Goh, Lei Yao, Yuan Gao:
A 16-channel TDM analog front-end with enhanced system CMRR for wearable dry EEG recording. 33-36 - Sheng-Ying Lin, Tsung-Hsien Lin:
An area-efficient amplifier-less digitally-controlled li-ion battery charger in 0.35μm CMOS. 37-40 - Da-Shin Lin, Hao-Ping Hong:
A 0.5V BJT-based CMOS thermal sensor in 10-nm FinFET technology. 41-44 - Chun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin:
An ultra-low power 169-nA 32.768-kHz fractional-N PLL. 45-48 - Long Xu, Johan H. Huijsing, Kofi A. A. Makinwa:
A 10kHz-BW 93.7dB-SNR chopped ΔΣ ADC with 30V input CM range and 115dB CMRR at 10kHz. 49-52 - Wei-Sung Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee:
An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique. 53-56 - Chih-Chan Tu, Feng-Wen Lee, Han-Chun Chen, Yu-Kai Wang, Tsung-Hsien Lin:
An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC. 57-60 - Anh-Tuan Do, Xin Liu:
25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme. 61-64 - Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou:
A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices. 65-68 - Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran:
A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. 69-72 - Myungguk Lee, Seungho Han, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links. 73-76 - Kuan-Lin Fu, Shen-Iuan Liu:
A 56Gbps PAM-4 optical receiver front-end. 77-80 - Guang Zhu, Quan Pan, John Zhuang, Charlie Zhi, C. Patrick Yue:
A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification. 81-84 - Masum Hossain, Aurangozeb, A. K. M. Delwar Hossain, Maruf Mohammad:
A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI. 85-88 - Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang:
A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. 89-92 - Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski:
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. 93-96 - Paul Stärke, Vincent Rieß, Corrado Carta, Frank Ellinger:
A 173-200 GHz quadrature voltage-controlled oscillator in 130 nm SiGe BiCMOS. 97-100 - Cuei-Ling Hsieh, Hong-Shen Chen, Hou-Ru Pan, Jenny Yi-Chun Liu:
A 67 GHz dual injection quadrature VCO with -182.9 dBc/Hz FOM in 90-nm CMOS. 101-104 - Yue Chen, Masoud Babaie, Robert Bogdan Staszewski:
A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanks. 104-108 - Yi-An Li, Monte Mar, Borivoje Nikolic, Ali M. Niknejad:
On-chip spur and phase noise cancellation techniques. 109-112 - Chi-Wei Liu, Ming-Jie Chung, Hui-Hsuan Lee, Pei-Chun Liao, Po-Hung Chen:
A single-inductor triple-input-triple-output (SITITO) energy harvesting interface with cycle-by-cycle source tracking and adaptive peak-inductor-current control. 113-116 - Karim Rawy, Taegeun Yoo, Tony T. Kim:
An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW. 117-120 - Chiao-Hung Cheng, Li-Chi Lin, Jian-He Lin, Ke-Horng Chen, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai:
A DVS-based burst mode with automatic entrance point control technique in DC-DC boost converter for wearable devices and IoT applications. 121-124 - Hassan Saif, Yongmin Lee, Minsun Kim, Hyeonji Lee, Muhammad Bilawal Khan, Yoonmyung Lee:
A wide load and voltage range switched-capacitor DC-DC converter with load-dependent configurability for DVS implementation in miniature sensors. 125-128 - Shao-Qi Chen, Yen-Ting Lin, Yu-Sheng Ma, Wen-Hau Yang, Ke-Horng Chen, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai:
A high efficiency and fast transient digital low-dropout assisted switched-capacitor converter for EMI-free Internet of Everything (IoE) systems. 129-132 - Ting Liao, Nien-An Lee, Chih-Cheng Hsieh:
A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique. 133-136 - Michele D'Urbino, Chao Chen, Zhao Chen, Zu-yao Chang, Jacco Ponte, Boris Lippe, Michiel A. P. Pertijs:
An element-matched band-pass delta-sigma ADC for ultrasound imaging. 137-140 - Taehoon Kim, Suhwan Kim:
A 12.1mW, 60dB SNR, 8-channel beamforming embedded SAR ADC for ultrasound imaging systems. 141-144 - Jaeeun Jang, Minseo Kim, Joonsung Bae, Hoi-Jun Yoo:
A 2.79-mW 0.5%-THD CMOS current driver IC for portable electrical impedance tomography system. 145-148 - Sun-a Kim, Kyoung-Yong Choi, Dae-Woong Park, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee:
0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing. 149-152 - Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-Young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon-Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. 153-156 - Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi:
MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage. 157-160 - Yoshiaki Deguchi, Ken Takeuchi:
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data. 161-164 - M. Sultan M. Siddiqui, Zhao Chuan Lee, Tony Tae-Hyoung Kim:
A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI. 165-168 - Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee:
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages. 169-172 - Feng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Cheng-Ying Chen, Jinshun Bi, Ming Liu, Meng-Fan Chang:
A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range. 173-176 - Meng-Hsiung Hung, Yi-Shing Shih, Chin-Fu Li, Wei-Kai Hong, Ming-Yeh Hsu, Chih-Hao Chen, Yu-Lun Chen, Chun-Wei Lin, Yuan-Hung Chung:
A reconfigurable dual-band WiFi/BT combo transceiver with integrated 2G/BT SP3T, LNA/PA achieving concurrent receiving and wide dynamic range transmitting in 40nm CMOS. 177-180 - Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa:
A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. 181-184 - M. Kumarasamy Raja, Zhao Bin, Dan Lei Yan, Hongbao Zhang, Wei Yi Lim, Leo John Chemmanda:
A -121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT. 185-188 - Tong Fang, Zhao-yang Liu, Liyuan Liu, Yuan-Yuan Li, Jun-qi Liu, Jian Liu, Nanjian Wu:
Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process. 189-192 - Chun-Yuan Chiu, Zhen-Cheng Zhang, Tsung-Hsien Lin:
A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOS. 193-196 - Van Loi Le, Juhui Li, Alan Chang, Tony T. Kim:
An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications. 197-200 - Mitsuhiko Igarashi, Yoshio Takazawa, Yasumasa Tsukamoto, Kan Takeuchi, Koji Shibutani:
NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator. 201-204 - Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang:
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications. 205-208 - Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang:
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS. 209-212 - Chen-Che Kao, Sung-En Hsieh, Chih-Cheng Hsieh:
A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization. 213-216 - Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta:
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. 217-220 - U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. 221-224 - Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang:
A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. 225-228 - Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun:
A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator. 229-232 - Chester Liu, Sung-Gun Cho, Zhengya Zhang:
A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. 233-236 - Jinmook Lee, Dongjoo Shin, Hoi-Jun Yoo:
A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications. 237-240 - Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto:
EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS. 241-244 - Suhwan Cho, Seongrim Choi, Junsik Woo, Ara Kim, Byeong-Gyu Nam:
A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces. 245-248 - Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique. 249-252 - Chun-Yu Lin, Tun-Ju Wang, Tsung-Hsien Lin:
A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS. 253-256 - Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim:
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface. 257-260 - Hae-Woong Yang, Ashkan Roshan-Zamir, Young-Hoon Song, Samuel Palermo:
A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter. 261-264 - Inhee Lee, Dennis Sylvester, David T. Blaauw:
Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systems. 265-268 - Saurabh Chaubey, Ramesh Harjani:
A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency. 269-272 - Masanobu Tsuji:
A 762-pW 16.3-ps resolution digital pulse width modulator using zooming phase-interpolator. 273-276 - Junmin Jiang, Liusheng Sun, Xu Zhang, Shing Hin Yuen, Xianbo Li, Wing-Hung Ki, C. Patrick Yue, Kei May Lau:
Fully-integrated AMLED micro display system with a hybrid voltage regulator. 277-280 - Aikaterini Papadopoulou, Vladimir M. Milovanovic, Borivoje Nikolic:
A low-voltage low-offset dual strong-arm latch comparator. 281-284 - Wei Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. 285-288 - Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn:
A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators. 289-292 - Young-Ha Hwang, Jun-Eun Park, Deog-Kyoon Jeong:
A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications. 293-296 - Miguel Gandara, Paridhi Gulati, Nan Sun:
A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration. 297-300 - Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto:
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. 301-304 - Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolic:
A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET. 305-308 - Amaravati Anvesha, Arijit Raychowdhury:
A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training. 309-312 - Jinho Han, Youngsu Kwon, Yong Cheol Peter Cho, Hoi-Jun Yoo:
A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics. 313-316 - Jianfu Lin, Zheng Song, Nan Qi, Woogeun Rhee, Baoyong Chi:
A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector. 317-320 - Shunli Ma, Jili Sheng, Ning Li, Junyan Ren:
A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. 321-324 - Jens Anders, Sebastian Bader, Markus Dietl, Puneet Sareen, G. Rombach, Sotirios Tambouris, Maurits Ortmanns:
A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. 325-328 - Suneui Park, Heein Yoon, Jaehyouk Choi:
An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration. 329-332
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last updated on 2025-01-15 20:52 CET by the dblp team
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