default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID41st ESSCIRC 2015: Graz, Austria
- Wolfgang Pribyl, Franz Dielacher, Gernot Hueber:
ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference, Graz, Austria, September 14-18, 2015. IEEE 2015, ISBN 978-1-4673-7470-5 - Jonas Hansryd
:
5G wireless communication beyond 2020. 1-3 - Giorgio Baccarani, Emanuele Baravelli, Elena Gnani, Antonio Gnudi, Susanna Reggiani:
Theoretical analyses and modeling for nanoelectronics. 4-9 - Barbara Stadlober, Esther Karner, Andreas Petritz, Alexander Fian, Mihai Irimia-Vladu:
Nature as microelectronic fab: Bioelectronics: Materials, transistors and circuits. 10-17 - Sandro Carrara:
New frontiers in digital health: Remote monitoring of animal and human metabolism on our smartphones and tablets. 18 - Borivoje Nikolic:
Simpler, more efficient design. 20-25 - Michiel Steyaert, Filip Tavernier, Hans Meyvaert, Athanasios Sarafianos, Nicolas Butzen:
When hardware is free, power is expensive! Is integrated power management the solution? 26-34 - Yann Deval:
RFIC design by mathematics for next generation wireless access. 35 - Antonio A. D'Amico, Marcello De Matteis, Stefano D'Amico, Claudio De Berti, Lorenzo Crespi, Andrea Baschirotto:
A 4th-order 100μA diode-C-based filter with 5dBm-IIP3 at the 24MHz cut-off frequency. 36-39 - Saeed Ghamari, Gabriele Tasselli, Cyril Botteron, Pierre-André Farine:
A wide tuning range 4 th-order Gm-C elliptic filter for wideband multi-standards GNSS receivers. 40-43 - Cecilia Gimeno, Carlos Sánchez-Azqueta, Erick Guerrero, Javier Aguirre, Concepción Aldea, Santiago Celma:
A 2.5-Gb/s multi-rate continuous-time adaptive equalizer for short reach optical links. 44-47 - Paul Brandl, Reinhard Enne, Horst Zimmermann:
Optical wireless receiver circuit with integrated APD and high background-light immunity. 48-51 - Hiroshi Uemura, Yoichiro Kurita, Hideto Furuyama:
12.5Gb/s optical driver and receiver ICs with double threshold AGC for SATA Out-of-Band transmission. 52-55 - Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation. 56-59 - Tong Zhang, Mazhareddin Taghivand, Jacques Christophe Rudell:
A 55-70GHz two-stage tunable polyphase filter with feedback control for quadrature generation with <2° and <0.32dB phase/amplitude imbalance in 28nm CMOS process. 60-63 - Domenico Pepe, Domenico Zito:
A 78.8-92.8 GHz 4-bit 0-360° active phase shifter in 28nm FDSOI CMOS with 2.3 dB average peak gain. 64-67 - Chao Liu, Qiang Li, Yihu Li, Xiang Li, Haitao Liu, Yong-Zhong Xiong:
An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips. 68-71 - Stefan Shopov, Sorin P. Voinigescu:
A 3×40Gb/s 28nm FDSOI CMOS front-end array with 10mVPP sensitivity and >4VPP output swing. 72-75 - Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa:
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. 76-79 - Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. 80-83 - Björn Debaillie, Barend van Liempd, Benjamin P. Hershberg, Jan Craninckx, Kari Rikkinen, D. J. van den Broek, Eric A. M. Klumperink, Bram Nauta:
In-band full-duplex transceiver technology for 5G mobile networks. 84-87 - Shailesh Kulkarni, Ibrahim Kazi, David Seebacher, Peter Singerl, Franz Dielacher, Wim Dehaene, Patrick Reynaert:
Multi-standard wideband OFDM RF-PWM transmitter in 40nm CMOS. 88-91 - Ying Chen, Yu Pei, Domine M. W. Leenaerts:
A fully integrated 30GHz 16-QAM single-channel phased array transmitter with 5.9% EVM at 6dB back-off. 92-95 - Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. 96-99 - Kyuho Jason Lee, Junyoung Park, Injoon Hong, Hoi-Jun Yoo:
Intelligent task scheduler with high throughput NoC for real-time mobile object recognition SoC. 100-103 - Seyed Mohammad Ali Zeinolabedin, Jun Zhou, Xin Liu, Tony T. Kim:
A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression. 104-107 - Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche:
28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. 108-111 - Mitsuhiko Igarashi, Kan Takeuchi, Takeshi Okagaki, Koji Shibutani, Hiroaki Matsushita, Koji Nii:
An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology. 112-115 - Sanu Mathew, David Johnston, Paul Newman, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. 116-119 - José Luis González, Vincent Puyal, Alexandre Siligaris, Clement Jany, Cedric Dehos:
A 45GHz/55GHz LO frequency selector for E-band transceivers based on switchable injection locked-oscillators in BiCMOS 55nm. 120-123 - Haikun Jia, Baoyong Chi, Zhihua Wang:
An 8.2 GHz triple coupling low-phase-noise class-F QVCO in 65nm CMOS. 124-127 - Yue Wu, Tianyu Jia, Bo Xia, Xinlong Ma, Li Kang, Xiaodong Yang:
Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits. 128-131 - Yihu Li, Wang Ling Goh, Yong-Zhong Xiong:
A 124 to 132.5 GHz frequency quadrupler with 4.4 dBm output power in 0.13μm SiGe BiCMOS. 132-135 - Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren:
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. 136-139 - Philipp Greiner, Jasmin Grosinger, Christoph Steffan, Gerald Holweg, Wolfgang Bösch:
Non-trimmable LC oscillator for all CMOS frequency control. 140-143 - Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang:
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. 144-147 - Hazar Yueksel, Lukas Kull, Andreas Burg, Matthias Braendli, Peter Buchmann, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl:
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. 148-151 - Yipeng Wang, Duona Luo, Quan Pan, Liwen Jing, Zhixin Li, C. Patrick Yue:
A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks. 152-155 - Krishna T. Settaluri, Sen Lin, Sajjad Moazeni, Erman Timurdogan, Chen Sun, Michele Moresco, Zhan Su, Yu-Hsin Chen, Gerald Leake, Douglas LaTulipe, Colin McDonough, Jeremiah Hebding, Douglas Coolbaugh, Michael Watts, Vladimir Stojanovic:
Demonstration of an optical chip-to-chip link in a 3D integrated electronic-photonic platform. 156-159 - Francesco Radice, Melchiorre Bruccoleri, Enrico Mammei, Matteo Bassi, Andrea Mazzanti:
A low-noise programmable-gain amplifier for 25 Gb/s multi-mode fiber receivers in 28nm CMOS FDSOI. 160-163 - Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx:
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. 164-167 - Aritra Banerjee, Lei Ding, Rahmi Hezar:
High efficiency multi-mode outphasing RF power amplifier in 45nm CMOS. 168-171 - Chuanwei Li, Antonio Liscidini:
A current re-use PA-VCO cell for low-power BLE transmitters. 172-175 - Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx:
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. 176-179 - Fan Yang, Philip K. T. Mok:
A 0.6-1V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500mA loading range in 65-nm CMOS. 180-183 - Juergen Wittmann, Alexander Barner, Thoralf Rosahl, Bernhard Wicht:
A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain. 184-187 - Meng-Wei Chien, Wen-Hau Yang, Ying-Wei Chou, Hsin-Chieh Chen, Wei-Chung Chen, Ke-Horng Chen, Chin-Long Wey, Shin-Chi Lai, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo:
Suppressing output overshoot voltage technique with 47.1mW/μs power-recycling rate and 93% peak efficiency DC-DC converter for multi-core processors. 188-191 - Anca Gabriela Vasilica, Vlad Anghel, Gheorghe Pristavu, Gheorghe Brezeanu:
Suppressing start-up time variation versus load current - Adaptive soft-start in boost LED drivers. 192-195 - Juan Pablo Duarte, Sourabh Khandelwal, Aditya Sankar Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan:
BSIM-CMG: Standard FinFET compact model for advanced circuit design. 196-201 - Christian C. Enz, Maria-Anna Chalkiadaki, Anurag Mangla:
Low-power analog/RF circuit design based on the inversion coefficient. 202-208 - Claudio De Berti, Piero Malcovati, Lorenzo Crespi, Andrea Baschirotto:
A 106.7-dB DR, 390-μW CT 3rd-order ΣΔ modulator for MEMS microphones. 209-212 - Chongjun Ding, Yiannos Manoli, Matthias Keller:
A 5.1mW 74dB DR CT ΔΣ modulator with quantizer intrinsic ELD compensation achieving 75fJ/conv.-step in a 20MHz BW. 213-216 - Amrith Sukumaran, Shanthi Pavan:
A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC. 217-220 - Xin Meng, Jinzhou Cao, Tao He, Yi Zhang, Gabor C. Temes, Mitsuru Aniya, Kazuki Sobue, Koichi Hamashita:
A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. 221-224 - Rudolf Ritter, Patrick Torta, Lukas Dörrer, Antonio Di Giandomenico, Stefan Herzinger, Maurits Ortmanns:
A multimode CT ΔΣ-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection. 225-228 - Masaki Yonekura, Hiroki Ishikuro:
I/Q mismatch compensation ΔΣ modulator using ternary capacitor rotation technique. 229-232 - Jacob Göppert, Yiannos Manoli:
Fully integrated start-up at 70 mV of boost converters for thermoelectric energy harvesting. 233-236 - Abhik Das, Yuan Gao, Tony Tae-Hyoung Kim:
A 76% efficiency boost converter with 220mV self-startup and 2nW quiescent power for high resistance thermo-electric energy harvesting. 237-240 - David Bol, El Hafed Boufouss, Denis Flandre, Julien De Vos:
A 0.48mm2 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage. 241-244 - Benjamin Saft, Eric Schaefer, Alexander Rolapp, Eckhard Hennig:
An ultra-low power capacitance extrema and ratio detector for electrostatic energy harvesters. 245-248 - Teruki Someya, Hiroshi Fuketa, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya:
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. 249-252 - Toru Kawajiri, Takahiro Moroto, Hiroki Ishikuro:
A low EMI SIDO wireless power transfer system with 10μsec response time. 253-256 - Tae-Kwang Jang, Seokhyeon Jeong, Myungjoon Choi, Wanyeong Jung, Gyouho Kim, Yen-Po Chen, Yejoong Kim, Wootaek Lim, Dennis Sylvester, David T. Blaauw:
FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node. 257-262 - Martijn F. Snoeij, Viola Schaffer, Sudarshan Udayashankar, Mikhail V. Ivanov:
An integrated fluxgate magnetometer for use in closed-loop/open-loop isolated current sensing. 263-266 - Yeo Myung Kim, Woojun Choi, Jaehoon Kim, Sanghoon Lee, Sangho Lee, Hyeongon Kim, Kofi A. A. Makinwa, Youngcheol Chae, Tae Wook Kim:
A 0.02mm2 embedded temperature sensor with ±2°C inaccuracy for self-refresh control in 25nm mobile DRAM. 267-270 - Mei-Chen Chuang, Chia-Liang Tai, Ying-Chih Hsu, Alan Roth, Eric G. Soenen:
A temperature sensor with a 3 sigma inaccuracy of ±2°C without trimming from -50°C to 150°C in a 16nm FinFET process. 271-274 - Zeyu Cai, Robert H. M. van Veldhoven, Annelies Falepin, Hilco Suy, Eric Sterckx, Kofi A. A. Makinwa, Michiel A. P. Pertijs:
A ratiometric readout circuit for thermal-conductivity-based resistive gas sensors. 275-278 - Ning Guo, Yipeng Huang, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok, Simha Sethumadhavan, Yannis P. Tsividis:
Continuous-time hybrid computation with programmable nonlinearities. 279-282 - Peng Chen, Xiongchuan Huang, Yao-Hong Liu, Ming Ding, Cui Zhou, Ao Ba, Kathleen Philips, Harmke de Groot, Robert Bogdan Staszewski:
Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs. 283-286 - Matthias Kuhl, Yiannos Manoli:
A 0.01 mm2 fully-differential 2-stage amplifier with reference-free CMFB using an architecture-switching-scheme for bandwidth variation. 287-290 - Hsiang-An Yang, Chao-Chang Chiu, Shin-Chi Lai, Jui-Lung Chen, Chih-Wei Chang, Che-Hao Meng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo:
120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. 291-294 - Tero Tikka, Kari Stadius, Jussi Ryynänen, Mikko Kaltiokallio:
A 0.8-3 GHz mixer-first receiver with on-chip transformer balun in 65-nm CMOS. 295-298 - Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström, Markus Törmänen, Henrik Sjöland, Pietro Andreani:
A 0.6-3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters. 299-302 - Nam-Seog Kim, Jan M. Rabaey:
A 3.1-10.6GHz wavelet-based dual-resolution spectrum sensing with harmonic rejection mixers. 303-306 - Alexandre Siligaris, Yogadissen Andee, Eric Mercier, Jose Moron Guerra, Jean-François Lampin, Guillaume Ducournau, Yves Quéré:
A 278 GHz heterodyne receiver with on-chip antenna for THz imaging in 65 nm CMOS process. 307-310 - Taimur Gibran Rabuske, Jorge R. Fernandes:
A 9-b 0.4-V charge-mode SAR ADC with 1.6-V input swing and a MOSCAP-only DAC. 311-314 - Md Shakil Akter, Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult:
A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction. 315-318 - Sameer Singh, Madhusudan Govindarajan, T. S. Venkatesh, William Evans, Ayushi Kansal, S. S. Murali:
A 23fJ/conv-step 12b 290MS/s time interleaved pipelined SAR ADC. 319-322 - Dong-Ryeol Oh, Jong-In Kim, Min-Jae Seo, Jin-Gwang Kim, Seung-Tak Ryu:
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. 323-326 - Koki Tanaka, Ryo Saito, Hiroki Ishikuro:
A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration. 327-330 - Khawar Sarfraz, Mansun Chan:
A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines. 331-334 - Ashish Kumar, G. S. Visweswaran, Kaushik Saha:
Low voltage error resilient SRAM using run-time error detection and correction. 335-338 - Mihail Jefremow, Doris Schmitt-Landsiedel, Thomas Kern, Martin Stiftinger, Christoph Roll:
Slope only sense amplifier with 4.5ns sense delay for 8Mbit memory sector, employing in situ current monitoring with 66% write speed improvement in 40nm embedded flash for automotive. 339-342 - Alexander Fritsch, Michael Kugel, Rolf Sautter, Dieter F. Wendel, Juergen Pille, Otto A. Torreiter, Shankar Kalyanasundaram, Daniel A. Dobson:
A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction. 343-346 - Silvian Spiridon, Han Yan, Hans Eberhart:
A linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-Based transmitters. 347 - Khaled Khalaf, Vojkan Vidojkovic, John R. Long, Piet Wambacq:
A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS. 348-351 - Nima Soltani, Hossein Kassiri, Hamed Mazhab-Jafari, Karim Abdelhalim, Roman Genov:
0.13μm CMOS 230Mbps 21pJ/b UWB-IR transmitter with 21.3% efficiency. 352-355 - Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski:
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. 356-359 - Hesong Xu, Matteo Perenzoni, Nicola Massari, Alberto Gola, Alessandro Ferri, David Stoppa:
A 30-ns recovery time, 11.5-nC input charge range, 16-channel read-out ASIC for PET application. 360-363 - Sahba Jahromi, Jussi-Pekka Jansson, Ilkka Nissinen, Jan Nissinen, Juha Kostamovaara:
A single chip laser radar receiver with a 9×9 SPAD detector array and a 10-channel TDC. 364-367 - Pietro Ciccarella, Marco Carminati, Giorgio Ferrari, Francesco Morichetti, Marco Sampietro:
32-Channel low-noise lock-in ASIC for non-invasive light detection in silicon photonics. 368-371 - Luca Sant, Andrea Fant, Snezana Stojanovic, Simone Fabbro, Jose Luis Ceballos:
A 13.2b optical proximity sensor system with 130klx ambient light rejection capable of heart rate and blood oximetry monitoring. 372-375 - Mehmet Batuhan Dayanik, Nicholas Collins, Michael P. Flynn:
A 28.5-33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution. 376-379 - Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa:
A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. 380-383 - Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong:
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. 384-387 - Raghavasimhan Thirunarayanan, David Ruffieux, Nicola Scolari, Christian C. Enz:
A ΣΔ based direct all-digital frequency synthesizer with 20 Mbps frequency modulation capability and 3μs startup latency. 388-391 - Dmytro Cherniak, Michael Aichner, Roberto Nonis, Nicola Da Dalt:
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. 392-395 - Jiawei Xu, Pieter Harpe, Julia Pettine, Chris Van Hoof, Refet Firat Yazicioglu:
A low power configurable bio-impedance spectroscopy (BIS) ASIC with simultaneous ECG and respiration recording functionality. 396-399 - Mehrdad A. Ghanad, Catherine Dehollain, Michael M. Green:
A 30 μW remotely-powered implant with time-based voltage regulation. 400-403 - Chao Chen, Zhao Chen, Zu-yao Chang, Michiel A. P. Pertijs:
A compact 0.135-mW/channel LNA array for piezoelectric ultrasound transducers. 404-407 - Sebastian Nessler, Maximilian Marx, Michael Maurer, Stefan Rombach, Yiannos Manoli:
A Continuous-Time Collocated Force-Feedback and Readout Front-End for MEM Gyroscopes. 408-411 - Norman Dodel, Stefan Keil, Andreas Wiemhofer, Malte Kortstock, Philipp Scholz, Uwe Kerst, Roland Thewes:
A BIST structure for the evaluation of the MOSFET gate dielectric interface state density in post-processed CMOS chips. 412-415
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-15 20:55 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
