default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID20th MICRO 1987: Colorado Springs, Colorado, USA
- Gearold R. Johnson:
Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987. ACM/IEEE 1987, ISBN 0-89791-250-0 - Hiroshi G. Okuno
, Nobuyasu Osato, Ikuo Takeuchi:
Firmware approach to fast Lisp interpreter. 1-11 - Patrick M. Lenders:
Distributed microprogramming. 12-14 - Emilio Luque, Joan Sorribes, Ana Ripoll:
Tuning architecture at run-time. 15-21 - Takanobu Baba, Hiroshi Minakawa, Kenzo Okuda:
A visual microprogramming system. 23-30 - W. J. Chen, G. N. Reddy:
A computer aided design automation system for developing microprogrammed processors: a design approach through HDLs. 31-35 - Thomas Pittman, Lester Bartel:
Computer architecture simulation using a register transfer language. 36-39 - Mark Harris:
Extending microcode compaction for real architectures. 40-53 - Jayaram Bhasker:
An algorithm for microcode compaction of VHDL behavioral descriptions. 54-58 - Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia:
Microcode compaction with timing constraints. 59-68 - Kemal Ebcioglu:
A compilation technique for software pipelining of loops with conditional jumps. 69-79 - Jack S. Walicki, John D. Laughlin:
Operation scheduling in reconfigurable, multifunction pipelines. 80-87 - Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia:
GURPR - a method for global software pipelining. 88-96 - Jayaram Bhasker, Tariq Samad:
Compacting MIMOLA microcode. 97-105 - Michael A. Howland, Robert A. Mueller, Philip H. Sweany:
Trace scheduling optimization in a retargetable microcode compiler. 106-114 - Vicki H. Allan, Robert A. Mueller:
Phase coupling for horizontal microcode generation. 115-125 - Lothar Nowak:
Graph based retargetable microcode compilation in the MIMOLA design system. 126-132 - Augustus K. Uht, Constantine D. Polychronopoulos, John F. Kolen:
On the combination of hardware and software concurrency extraction methods. 133-141 - Onat Menzilcioglu:
A case study in using two-level control stores. 142-146 - David W. Archer:
The instruction parsing microarchitecture of the CVAX microprocessor. 147-153 - Wen-mei W. Hwu, Yale N. Patt:
Exploiting horizontal and vertical concurrency via the HPSm microprocessor. 154-161 - James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt:
On tuning the microarchitecture of an HPS implementation of the VAX. 162-167 - Stephen W. Melvin, Yale N. Patt:
SPAM: a microcode based tool for tracing operating system events. 168-171
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-10 21:51 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
