default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID5th RSP 1994: Grenoble, France
- Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, RSP 1994, Grenoble, France, June 20-23, 1994. IEEE Computer Society 1994, ISBN 0-8186-5885-1
- Mark A. Richards:
The Rapid Prototyping of Application Specific Signal Processors (RASSP) program: overview and status. 1-6 - Marc Engels, Teresa H. Meng:
Rapid prototyping of a real-time video encoder. 8-15 - Richard W. Wieler, Zaifu Zhang, Robert D. McLeod:
Using an FPGA based computer as a hardware emulator for built-in self-test structures. 16-21 - Evaggelinos P. Mariatos, Michael K. Birbas, Alexios N. Birbas:
A reconfigurable DSP board based on CORDIC elements. 22-25 - David L. Andrews
, Andrew Wheeler, Barry Wealand, Cliff Kancler:
Rapid prototype of an SIMD processor array (using FPGA's). 28-33 - C. Papadopoulos, Alex Maniatopoulos, Theodore Antonakopoulos, Vassilios Makios:
A real-time test-bed for prototyping cell-based communication networks. 34-39 - Glaucia D. F. Azevedo, Helio Azevedo, Mário Jino:
ProTR: a tool for real-time systems development. 42-51 - William El Kaim, Fabrice Kordon:
An integrated framework for rapid system prototyping and automatic code distribution. 52-61 - Danny Dolev, Ray Strong, Ed Wimmers:
Experience with RAPID prototypes. 62-72 - Tarek Ben Ismail, Mohamed Abid, Kevin O'Brien, Ahmed Amine Jerraya:
An approach for hardware-software codesign. 73-80 - Cory S. Myers, Paul D. Fiore, J. P. Letellier:
Rapid development of signal processors and the RASSP program. 82-89 - Rudy Lauwereins, Piet Wauters, Marleen Adé, J. A. Peperstraete:
Geometric parallelism and cyclo-static data flow in GRAPE-II. 90-107 - Marleen Adé, Rudy Lauwereins, J. A. Peperstraete:
Buffer memory requirements in DSP applications. 108-123 - W. Y. Lo, Chiu-sing Choy, Cheong-Fat Chan:
Hardware emulation board based on FPGAs and programmable interconnections. 126-130 - Arindam Saha, Rangasayee Krishnamurthy:
Some design issues in multi-chip FPGA implementation of DSP algorithms. 131-140 - Michel Courtoy:
Project Spinnaker: a new generation of rapid prototyping system. 141-144 - John Daniel Sterling Babcock, Apostolos Dollas:
Extended VHDL for the rapid prototyping of systems with synthesizable and nonsynthesizable subsystems. 146-152 - Dominique Lavenier, Roderick McConnell:
From behavioral to RTL models: an approach. 153-161 - Jean-Yves Brunel, Ivan Augé, Marc Hervieu, Philippe Bourquin, Philippe Renaud:
Quantitative design of a scalable microsystem using ALMA: the example of the dictionary machine. 162-165 - Michele Missikoff, Marco Toiati:
Safe rapid prototyping of object-oriented database applications. 168-176 - Stephen E. Cross, Richard Estrada:
DART: an example of accelerated evolutionary development. 177-183 - Ammar Attoui, Michel Schneider:
A formal approach based on the rewriting logic for prototyping distributed information systems. 184-19 - Luigi Carro, Altamiro A. Suzim:
Algorithms and architectures to computational systems implementation. 196-204 - Polen Kission, Hong Ding, Ahmed Amine Jerraya:
Accelerating the design process by using architectural synthesis. 205-212 - Gary E. Fisher:
Rapid system prototyping in an open system environment. 213-219
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-27 20:51 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
