default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 41
Volume 41, Number 1, January 2008
- Nadine Azémard, Philippe Maurine, Johan Vounckx:
Editorial. 1 - Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii
, Enrico Macii, Massimo Poncino:
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. 2-8 - B. Chung, J. B. Kuo:
Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application. 9-16 - Abbas Sheibanyrad, Alain Greiner:
Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures. 17-26 - Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
Crosstalk fault modeling in defective pair of interconnects. 27-37 - David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo:
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. 38-48
- Ghassem Jaberipur, Behrooz Parhami:
Constant-time addition with hybrid-redundant numbers: Theory and implementations. 49-64 - Nozar Tabrizi, Nader Bagherzadeh:
An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator. 65-75 - Chi-Ying Tsui, Robert Yi-Ching Au, Ricky Yiu-kee Choi:
Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping. 76-86 - Dimitrios Voudouris, Marinos Sampson, George K. Papakonstantinou:
Exact ESCT minimization for functions of up to six input variables. 87-105 - Chiou-Yng Lee:
Low-complexity bit-parallel systolic multipliers over GF(2m). 106-112 - Meng Yang, Lingli Wang, Jiarong Tong, A. E. A. Almaini:
Techniques for dual forms of Reed-Muller expansion conversion. 113-122 - Cao Cao, Bengt Oelmann:
Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory. 123-134 - Vassilios A. Chouliaras, Vincent M. Dwyer, Shahrukh Agha, José L. Núñez-Yáñez, Dionysios I. Reisis, Konstantinos Nakos, Konstantinos Manolopoulos:
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study. 135-152 - Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan:
Large scale P/G grid transient simulation using hierarchical relaxed approach. 153-160
Volume 41, Number 2, February 2008
- Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni:
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver. 161-170 - Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. 171-182 - Hamed Aminzadeh, Mohammad Danaie, Reza Lotfi:
Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters. 183-192 - Meng-Chun Lin, Lan-Rong Dung:
On VLSI design of rank-order filtering using DCRAM architecture. 193-209 - Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGaughy:
An efficient terminal and model order reduction algorithm. 210-218 - Ireneusz Brzozowski, Andrzej Kos:
A new approach to power estimation and reduction in CMOS digital circuits. 219-237 - Ewout Martens, Georges G. E. Gielen:
Classification of analog synthesis tools based on their architecture selection mechanisms. 238-252 - Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
On optimal ordering of signals in parallel wire bundles. 253-268 - Alonso Morgado, V. J. Rivas, Rocío del Río, Rafael Castro-López, Francisco V. Fernández, José M. de la Rosa:
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK. 269-280 - Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos:
Allocation heuristics and defragmentation measures for reconfigurable systems management. 281-296 - Ndubuisi Ekekwe, Ralph Etienne-Cummings, Peter Kazanzides:
A wide speed range and high precision position and velocity measurements chip with serial peripheral interface. 297-305 - Jill H. Y. Law, Evangeline F. Y. Young:
Multi-bend bus driven floorplanning. 306-316
Volume 41, Number 3, May 2008
- Francisco V. Fernández:
Editorial. 317-318
- Dennis Sylvester, Kanak Agarwal, Saumil Shah:
Variability in nanometer CMOS: Impact, analysis, and minimization. 319-339 - David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli:
Network-on-Chip design and synthesis outlook. 340-359
- Lerong Cheng, Xiaoyu Song, Guowu Yang, William N. N. Hung, Zhiwei Tang, Shaodi Gao:
A fast congestion estimator for routing with bounded detours. 360-370 - Apostolos P. Fournaris, Odysseas G. Koufopavlou:
Versatile multiplier architectures in GF(2k) fields using the Montgomery multiplication algorithm. 371-384 - Tyler L. Brandon, Robert Hang, Gary Block, Vincent C. Gaudet, Bruce F. Cockburn, Sheryl L. Howard, Christian Giasson, Keith Boyle, Paul Goud, Siavash Sheikh Zeinoddin, Anthony Rapley, Stephen Bates, Duncan G. Elliott, Christian Schlegel:
A scalable LDPC decoder ASIC architecture with bit-serial message exchange. 385-398 - Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker:
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. 399-412 - Tom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan:
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. 413-425 - Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. 426-438 - Gaetano Palumbo, Melita Pennisi:
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison. 439-446 - Slawomir Mikula, Gilbert De Mey, Andrzej Kos:
Asynchronous control of modules activity in integrated systems for reducing peak temperatures. 447-458
Volume 41, Number 4, July 2008
- Arkan Abdulrahman, Spyros Tragoudas:
Low-power multi-core ATPG to target concurrency. 459-473 - Hau T. Ngo, Vijayan K. Asari, Ming Z. Zhang, Li Tao:
Design of a systolic-pipelined architecture for real-time enhancement of color video stream based on an illuminance-reflectance model. 474-488 - Vasilis F. Pavlidis, Eby G. Friedman:
Timing-driven via placement heuristics for three-dimensional ICs. 489-508 - Jonathan R. Haigh, Lawrence T. Clark:
High performance set associative translation lookaside buffers for low power microprocessors. 509-523 - Mariagrazia Graziano, Gianluca Piccinini:
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks. 524-538 - Jaime Ramírez-Angulo, Milind S. Sawant, Antonio J. López-Martín, Ramón González Carvajal:
A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-amps. 539-543 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
SafeResynth: A new technique for physical synthesis. 544-556 - Higinio Mora Mora, Jerónimo Mora Pascual, José-Luis Sánchez-Romero, Juan Manuel García Chamizo:
Partial product reduction by using look-up tables for M×N multiplier. 557-571
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-09 14:59 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
