default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Journal of Solid-State Circuits, Volume 57
Volume 57, Number 1, January 2022
- Amir Amirkhany
, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito:
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). 3-5 - Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, Savyasaachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yoav Segal, Yongping Fan, Peng Li, Frank O'Mahony:
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. 6-20 - Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. 21-31 - James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan, Davide Tonietto:
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. 32-43 - Hao Li, Chun-Ming Hsu, Jahnavi Sharma, James E. Jaussi, Ganesh Balamurugan:
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS. 44-53 - Atharav Atharav, Behzad Razavi:
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS. 54-67 - Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. 68-79 - Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. 80-89 - Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe:
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. 90-102 - Xinning Liu, Xiaomin Li, Huanqing Zhang, Chenyang Li, Lizheng Ren, Qing Chen, Yibo Xu, Jun Yang:
SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. 103-114 - Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei:
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. 115-126 - Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. 127-139 - Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woorham Bae, Sean Huang, Vladimir M. Milovanovic, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic:
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. 140-152 - Sachin Taneja, Viveka Konandur Rajanna, Massimo Alioto:
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security. 153-166 - Archisman Ghosh, Debayan Das, Josef Danial, Vivek De, Santosh Ghosh, Shreyas Sen:
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation. 167-181 - Sae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang:
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. 182-197 - Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma:
Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing. 198-211 - Jihyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha:
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. 212-223 - Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong:
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling. 224-235 - Taejoong Song, Hoonki Kim, Woojin Rim, Hakchul Jung, Changnam Park, Inhak Lee, Sanghoon Baek, Jonghoon Jung:
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. 236-244 - Vijaya Kumar Purushothaman, Eric A. M. Klumperink, Roel Plompen, Bram Nauta:
Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain. 245-259 - Jingzhi Zhang, Yu Peng, Kai Kang:
Analysis and Design of High-Harmonic-Rejection Multi-Ratio mm-Wave Frequency Multipliers. 260-277 - Sanfeng Zhang, Xiong Zhou, Chen Gao, Qiang Li:
A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication. 278-289 - Amir Bozorg, Robert Bogdan Staszewski:
A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters. 290-301 - Pengfei Zhai, Zheng Zhu, Xiong Zhou, Yan Cai, Fan Zhang, Qiang Li:
An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization. 302-311 - Farhad Bozorgi, Melchiorre Bruccoleri, Elham Rahimi, Matteo Repossi, Francesco Svelto, Andrea Mazzanti:
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology. 312-322 - Sumon Kumar Bose, Deepak Singla, Arindam Basu:
A 51.3-TOPS/W, 134.4-GOPS In-Memory Binary Image Filtering in 65-nm CMOS. 323-335
Volume 57, Number 2, February 2022
- Susnata Mondal, Larry Richard Carley, Jeyanandh Paramesh:
Dual-Band, Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems. 339-355 - Yun Wang, Dongwon You, Xi Fu, Takeshi Nakamura, Ashbir Aviat Fadila, Teruki Someya, Atsuhiro Kawaguchi, Junjun Qiu, Jian Pang, Kiyoshi Yanagisawa, Bangan Liu, Yuncheng Zhang, Haosheng Zhang, Rui Wu, Shunichiro Masaki, Daisuke Yamazaki, Atsushi Shirane, Kenichi Okada:
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. 356-370 - Xingcun Li, Wenhua Chen, Shuyang Li, Yunfan Wang, Fei Huang, Xiang Yi, Ruonan Han, Zhenghe Feng:
A High-Efficiency 142-182-GHz SiGe BiCMOS Power Amplifier With Broadband Slotline-Based Power Combining Technique. 371-384 - Siwei Li, Zhe Zhang, Bhaskara Rupakula, Gabriel M. Rebeiz:
An Eight-Element 140-GHz Wafer-Scale IF Beamforming Phased-Array Receiver With 64-QAM Operation in CMOS RFSOI. 385-399 - Liang Gao, Chi Hou Chan:
A 0.45-THz 2-D Scalable Radiator Array With 28.2-dBm EIRP Using an Elliptical Teflon Lens. 400-412 - Haijun Shao, Gengzhen Qi, Pui-In Mak, Rui Paulo Martins:
A 1.7-3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP₃ and 3.4-4.8 dB NF. 413-422 - Yi-Zhi Qiu, Shih-Hsiung Chien, Tai-Haur Kuo:
A 0.4-mA-Quiescent-Current, 0.00091%-THD+N Class-D Audio Amplifier With Low-Complexity Frequency Equalization for PWM-Residual- Aliasing Reduction. 423-433 - Li Xu, Taekwang Jang, Jongyup Lim, Kyojin David Choo, David T. Blaauw, Dennis Sylvester:
A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection. 434-451 - Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski:
A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. 452-464 - Jason Remple, Andrea Panigada, Ian Galton:
An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs. 465-479 - Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Jaehyouk Choi:
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. 480-491 - Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie:
A Low-Jitter and Low-Spur Charge-Sampling PLL. 492-504 - Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino:
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. 505-517 - Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski:
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. 518-534 - Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. 535-545 - Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. 546-561 - Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim:
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. 562-572 - Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong:
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. 573-585 - Kwantae Kim, Sangyeob Kim, Hoi-Jun Yoo:
Design of Sub-10-μW Sub-0.1% THD Sinusoidal Current Generator IC for Bio-Impedance Sensing. 586-595 - Yizhak Shifman, Inbal Stanger, Netanel Shavit, Ramiro Taco, Alexander Fish, Joseph Shor:
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic. 596-608 - Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang:
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. 609-624 - Minsu Kim, Muqing Liu, Luke R. Everson, Chris H. Kim:
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process. 625-638 - Sae Kyu Lee, Paul N. Whatmough, Marco Donato, Glenn G. Ko, David Brooks, Gu-Yeon Wei:
SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators. 639-650 - Roel Uytterhoeven, Wim Dehaene:
Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor. 651-660 - Dongseok Im, Donghyeon Han, Sanghoon Kang, Hoi-Jun Yoo:
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling Layer Prediction. 661-670 - Dawei Ye, Rongjin Xu, Chuanjin Richard Shi:
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". 671
Volume 57, Number 3, March 2022
- Mark S. Oude Alink, Farhana Sheikh:
Guest Editorial 2021 Custom Integrated Circuits Conference. 675-676 - Boyu Shen, Soumya Bose, Matthew L. Johnston:
A Frequency-Locked Oscillator Using Complex RC Impedance IQ-Balancing. 677-687 - Hao Luo, Somnath Kundu, Timo Huusari, Sarah Shahraini, Eduardo Alban, Jason Mix, Nasser A. Kurd, Mohamed Abdel-Moneum, Brent R. Carlton:
A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS. 688-697 - Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu:
A 3.2-GHz 405 fsrms Jitter -237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer. 698-708 - Menglian Zhao, Yibo Zhao, Huajun Zhang, Yaopeng Hu, Yuanxin Bao, Le Ye, Wanyuan Qu, Zhichao Tan:
A 4-μW Bandwidth/Power Scalable Delta-Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers. 709-718 - Weiyu Leng, Asad A. Abidi, Sraavan R. Mundlapudi, Hooman Darabi, Debopriyo Chowdhury, Ali Afsahi, Sida Li:
Envelope Tracking Supply Modulator with Trellis-Search-Based Switching and 160-MHz Capability. 719-733 - Yuting Shen, Hanyue Li, Haoming Xin, Eugenio Cantatore, Pieter Harpe:
A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques. 734-744 - Yanbo Zhang, Jin Zhang, Shubin Liu, Ruixue Ding, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. 745-756 - Mozhgan Mansuri, Rajesh Inti, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li, Bryan Casper, James E. Jaussi:
A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS. 757-766 - Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi:
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. 767-780 - Ki Yong Kim, David Z. Pan, Ranjit Gharpurey:
A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control. 781-792 - Mansour Taghadosi, Hossein Kassiri:
A Calibration-Free Energy-Efficient IC for Link-Adaptive Real-Time Energy Storage Optimization of CM Inductive Power Receivers. 793-802 - Mohsen Mortazavi, Yiyu Shen, Dieuwert P. N. Mul, Leo C. N. de Vreede, Marco Spirito, Masoud Babaie:
A Four-Way Series Doherty Digital Polar Transmitter at mm-Wave Frequencies. 803-817 - Zhanghao Yu, Joshua C. Chen, Yan He, Fatima T. Alrashdan, Benjamin W. Avants, Amanda Singer, Jacob T. Robinson, Kaiyuan Yang:
Magnetoelectric Bio-Implants Powered and Programmed by a Single Transmitter for Coordinated Multisite Stimulation. 818-830 - Nirmoy Modak, Debayan Das, Mayukh Nath, Baibhab Chatterjee, K. Gaurav Kumar, Shovan Maity, Shreyas Sen:
EQS Res-HBC: A 65-nm Electro-Quasistatic Resonant 5-240 μW Human Whole-Body Powering and 2.19 μW Communication SoC With Automatic Maximum Resonant Power Tracking. 831-844 - Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. 845-857 - Yuqi Su, Junjie Mu, Hyunjoon Kim, Bongjin Kim:
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems. 858-868 - Han Hao, Hangxing Liu, Jan Van der Spiegel, Firooz Aflatouni:
A Wireless Somatosensory Feedback System Using Human Body Communication. 869-881 - Van-Son Trinh, Jung-Dong Park:
An 85-GHz Power Amplifier Utilizing a Transformer-Based Power Combiner Operating Beyond the Self-Resonance Frequency. 882-891 - Kyung-Sik Choi, Jinho Ko, Keun-Mok Kim, Jusung Kim, Sang-Gug Lee:
A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA. 892-905 - Shiyu Su, Mike Shuo-Wei Chen:
SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. 906-916 - Anjana Dissanayake, Henry L. Bishop, Steven M. Bowers, Benton H. Calhoun:
A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver. 917-931 - Tae-Jin Kim, Jae-Woo Park, Hyun-Wook Lim, Jae-Youl Lee, Jung-Hoon Chun:
An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires. 932-941 - Min Kyu Song, Lei Chen, Joseph Sankman, Dongsheng Brian Ma:
On-Chip HV Bootstrap Gate Driving for GaN Compatible Power Circuits Operating Above 10 MHz. 942-952 - Nader Sherif Kassem Fathy, Jiannan Huang, Patrick P. Mercier:
A Digitally Assisted Multiplexed Neural Recording System With Dynamic Electrode Offset Cancellation via an LMS Interference-Canceling Filter. 953-964 - Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon:
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees. 965-977
Volume 57, Number 4, April 2022
- Yusuke Oike, Borivoje Nikolic:
Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI Circuits. 983-985 - Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. 986-998 - Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Ji-Hoon Kim, Donghyeon Han, Hoi-Jun Yoo:
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer. 999-1012 - Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina:
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. 1013-1026 - Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas, Geethan Karunaratne, Matthias Brändli, Feng Liu, Abhairaj Singh, Silvia M. Müller, Urs Egger, Anastasios Petropoulos, Theodore Antonakopoulos, Kevin Brew, Samuel Choi, Injo Ok, Fee Li Lie, Nicole Saulnier, Victor Chan, Ishtiaq Ahsan, Vijay Narayanan, S. R. Nandakumar, Manuel Le Gallo, Pier Andrea Francese, Abu Sebastian, Evangelos Eleftheriou:
HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs. 1027-1038 - Keonhee Cho, Heekyung Choi, In Jun Jung, Ji Sang Oh, Tae Woo Oh, Ki-Ryong Kim, Giseok Kim, Taemin Choi, Changsu Sim, Taejoong Song, Seong-Ook Jung:
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling. 1039-1048 - Miaolin Zhang, Lian Zhang, Chne-Wuen Tsai, Jerald Yoo:
A Patient-Specific Closed-Loop Epilepsy Management SoC With One-Shot Learning and Online Tuning. 1049-1060 - Jongyup Lim, Jungho Lee, Eunseong Moon, Michael Barrow, Gabriele Atzeni, Joseph G. Letner, Joseph T. Costello, Samuel R. Nason, Paras R. Patel, Yi Sun, Parag G. Patil, Hun-Seok Kim, Cynthia A. Chestek, Jamie Phillips, David T. Blaauw, Dennis Sylvester, Taekwang Jang:
A Light-Tolerant Wireless Neural Recording IC for Motor Prediction With Near-Infrared-Based Power and Data Telemetry. 1061-1074 - Ji-Seon Paek, Dong-Su Kim, Jae-Yeol Han, Young-Hwan Choo, Jun-Suk Bang, Seungchan Park, Jongbeom Baek, Takahiro Nomiyama, Ik-Hwan Kim, Jongwoo Lee:
Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front End. 1075-1089 - Nachiket V. Desai, Han Wui Then, Jingshu Yu, Harish K. Krishnamurthy, William J. Lambert, Nicolas Butzen, Sheldon Weng, Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors. 1090-1099 - Sanjeev Tannirkulam Chandrasekaran, Sumukh Prashant Bhanushali, Stefano Pietri, Arindam Sanyal:
OTA-Free 1-1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC. 1100-1111 - Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx:
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. 1112-1124 - Min-Woong Seo, Myunglae Chu, Hyun-Yong Jung, Suksan Kim, Jiyoun Song, Daehee Bae, Sanggwon Lee, Junan Lee, Sung-Yong Kim, Jongyeon Lee, Minkyung Kim, Gwi-Deok Lee, Heesung Shim, Changyong Um, Changhwa Kim, In-Gyu Baek, Doowon Kwon, Hongki Kim, Hyuksoon Choi, Jonghyun Go, JungChak Ahn, Jaekyu Lee, Chang-Rok Moon, Kyupil Lee, Hyoung-Sub Kim:
2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory. 1125-1137 - Rohit Rothe, Minchang Cho, Kyojin Choo, Seokhyeon Jeong, Sechang Oh, Jungho Lee, Dennis Sylvester, David T. Blaauw:
A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End. 1138-1152 - Huajun Zhang, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan:
A -121.5-dB THD Class-D Audio Amplifier With 49-dB LC Filter Nonlinearity Suppression. 1153-1161 - Wei Deng, Zipeng Chen, Haikun Jia, Angxiao Yan, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi:
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation. 1162-1174 - Sujin Park, Ji-Hwan Seol, Li Xu, SeongHwan Cho, Dennis Sylvester, David T. Blaauw:
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance. 1175-1186 - Jahnavi Sharma, Zhe Xuan, Hao Li, Taehwan Kim, Ranjeet Kumar, Meer N. Sakib, Chun-Ming Hsu, Chaoxuan Ma, Haisheng Rong, Ganesh Balamurugan, James E. Jaussi:
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS. 1187-1198 - Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans:
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. 1199-1210 - Michihiro Ide, Atsushi Shirane, Kiyoshi Yanagisawa, Dongwon You, Jian Pang, Kenichi Okada:
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer. 1211-1223 - Hieu Minh Nguyen, Jeffrey Sean Walling, Anding Zhu, Robert Bogdan Staszewski:
A mm-Wave Switched-Capacitor RFDAC. 1224-1238
Volume 57, Number 5, May 2022
- Domine M. W. Leenaerts:
Guest Editorial Introduction to the Special Section on the 2021 RFIC Symposium. 1243 - Naga Sasikanth Mannem, Tzu-Yuan Huang, Elham Erfani, Sensen Li, David Joseph Munzer, Matthieu R. Bloch, Hua Wang:
A 25-34-GHz Eight-Element MIMO Transmitter for Keyless High Throughput Directionally Secure Communication. 1244-1256 - Venumadhav Bhagavatula, Fan Zhang, Che-Chun Kuo, Anirban Sarkar, Ashutosh Verma, Tienyu Chang, Xiaohua Yu, Daeyoung Yoon, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control. 1257-1266 - Hyun-Chul Park, Seokhyeon Kim, Jooseok Lee, Junho Jung, Seungjae Baek, Taewan Kim, Daehyun Kang, Donggyu Minn, Sung-Gi Yang:
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs. 1267-1279 - Abdulrahman A. Alhamed, Gökhan Gültepe, Gabriel M. Rebeiz:
A Multi-Band 16-52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14-15.4-dBm Psat for 5G NR FR2 Operation. 1280-1290 - Tolga Dinc, Sachin Kalia, Siraj Akhtar, Baher Haroun, Benjamin Cook, Swaminathan Sankaran:
High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation. 1291-1299 - Xinyan Tang, Johan Nguyen, Giovanni Mangraviti, Zhiwei Zong, Piet Wambacq:
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS. 1300-1313 - Yunfan Wang, Wenhua Chen, Xingcun Li, Jiaxian Chen, Long Chen, Fei Huang, Shuyang Li, Zhaozhuo Wang:
Highly Efficient Terahertz Beam-Steerable Integrated Radiator Based on Tunable Boundary Conditions. 1314-1331 - Siwei Li, Gabriel M. Rebeiz:
High Efficiency D-Band Multiway Power Combined Amplifiers With 17.5-19-dBm Psat and 14.2-12.1% Peak PAE in 45-nm CMOS RFSOI. 1332-1343 - Muhammad Ibrahim Wasiq Khan, Jongchan Woo, Xiang Yi, Mohamed I. Ibrahim, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Ruonan Han:
A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping. 1344-1357 - Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. 1358-1371 - Sachin Kalia, Salvatore Finocchiaro, Tolga Dinc, Bichoy Bahr, Ashwin Raghunathan, Gerd Schuppener, Siraj Akhtar, Tobias Fritz, Baher Haroun, Benjamin Cook, Swaminathan Sankaran:
A Sub-100 Fs RMSjitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference. 1372-1384 - Kejian Shi, Hooman Darabi, Asad A. Abidi:
Design and Analysis of an Electrical Balance Duplexer With Independent and Concurrent Dual-Band TX-RX Isolation. 1385-1396 - Saeid Daneshgar, Hao Li, Taehwan Kim, Ganesh Balamurugan:
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS. 1397-1408 - Guillaume Tochou, Robin Benarrouch, David Gaidioz, Andreia Cathelin, Antoine Frappé, Andreas Kaiser, Jan M. Rabaey:
A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS. 1409-1420 - Christopher Sutardja, Ajay Singhvi, Aidan Fitzpatrick, Andreia Cathelin, Amin Arbabian:
Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable Thermoacoustic Imaging. 1421-1431 - Anoop Narayan Bhat, Ronan A. R. van der Zee, Bram Nauta:
A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving p-p Output Swing Over 0.01-5.4-GHz for Direct RF Sampling Applications. 1432-1445 - Yiyu Shen, Rob Bootsman, Morteza S. Alavi, Leo C. N. de Vreede:
A Wideband IQ-Mapping Direct-Digital RF Modulator for 5G Transmitters. 1446-1456 - Shi Bu, Sudhakar Pamarti:
A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation. 1457-1469 - Amr Khashaba, Junheng Zhu, Nilanjan Pal, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors. 1470-1479 - Hongshuai Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration. 1480-1491 - Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, Chulwoo Kim:
A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique. 1492-1503 - Yi-Wei Huang, Tai-Haur Kuo:
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC-DC Converters. 1504-1516 - Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi, Ryuichi Fujimoto:
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. 1517-1526 - Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand:
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. 1527-1541 - Huiyu Mo, Wenping Zhu, Wenjing Hu, Qiang Li, Ang Li, Shouyi Yin, Shaojun Wei, Leibo Liu:
A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. 1542-1557
Volume 57, Number 6, June 2022
- Xiao Yang, Yin-Shan Huang, Liang Zhou, Zhe Zhao, Dong-Xin Ni, Cheng-Rui Zhang, Junfa Mao, Jiangan Han, Xu Cheng, Xianjin Deng:
Low-Loss Heterogeneous Integrations With High Output Power Radar Applications at W-Band. 1563-1577 - Matan Gal-Katziri, Craig Ives, Armina Khakpour, Ali Hajimiri:
Optically Synchronized Phased Arrays in CMOS. 1578-1593 - Mohammad Barzgari, Ali Ghafari, Amir Nikpaik, Ali Medi:
Even-Harmonic Class-E CMOS Oscillator. 1594-1609 - Yicheng Li, Yun Yin, Diyang Zheng, Xianglong Jia, Jie Lin, Fu Gao, Yiting Zhu, Liang Xiong, Na Yan, Ye Lu, Hongtao Xu:
A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement. 1610-1622 - Bahareh Hadidian, Farzad Khoeini, S. M. Hossein Naghavi, Andreia Cathelin, Ehsan Afshari:
A 220-GHz Energy-Efficient High-Data-Rate Wireless ASK Transmitter Array. 1623-1634 - Siwei Li, Zhe Zhang, Gabriel M. Rebeiz:
An Eight-Element 136-147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation. 1635-1648 - Ahmet T. Erdogan, Tarek Al Abbas, Neil Finlayson, Charlotte Hopkinson, István Gyöngy, Oscar Almer, Neale A. W. Dutton, Robert K. Henderson:
A High Dynamic Range 128 × 120 3-D Stacked CMOS SPAD Image Sensor SoC for Fluorescence Microendoscopy. 1649-1660 - Yi Luo, Shahriar Mirabbasi:
A 30-fps 192 × 192 CMOS Image Sensor With Per-Frame Spatial-Temporal Coded Exposure for Compressive Focal-Stack Depth Sensing. 1661-1672 - Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. 1673-1683 - Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski:
A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC. 1684-1699 - R. Gautam, Saurabh Saxena:
A 1.12-1.91 mW/GHz 2.46-4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS. 1700-1711 - Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong:
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. 1712-1722 - Simone Mattia Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. 1723-1735 - Dongseok Shin, Hyung Seok Kim, Chuanchang Liu, Priya Wali, Savyasaachi Keshava Murthy, Yongping Fan:
A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications. 1736-1748 - Yue Chen, Jiang Gong, Robert Bogdan Staszewski, Masoud Babaie:
A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and pp Supply Ripple. 1749-1764 - Yuming He, Johan H. C. van den Heuvel, Paul Mateman, Erwin Allebes, Stefano Traferro, Johan Dijkhuis, Keigo Bunsen, Peter Vis, Arjan Breeschoten, Yao-Hong Liu, Tomohiro Matsumoto, Christian Bachmann:
An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation. 1765-1775 - Zhaowen Wang, Yudong Zhang, Yuka Onizuka, Peter R. Kinget:
Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL. 1776-1787 - Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino:
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology. 1788-1799 - Liang Fang, Ping Gui:
A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating Chopping Ripples. 1800-1811 - Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn:
An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor. 1812-1823 - Haoran Pu, Omid Malekzadeh-Arasteh, Ahmad Reza Danesh, Zoran Nenadic, An H. Do, Payam Heydari:
A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression. 1824-1840 - Xiangyu Mao, Yan Lu, Rui Paulo Martins:
A Scalable High-Current High-Accuracy Dual-Loop Four-Phase Switching LDO for Microprocessors. 1841-1853 - Ziyu Xia, Jason T. Stauth:
A Cascaded Hybrid Switched-Capacitor DC-DC Converter Capable of Fast Self Startup for USB Power Delivery. 1854-1864 - Seneke Chamith Chandrarathna, Jong-Wook Lee:
A Self-Resonant Boost Converter for Photovoltaic Energy Harvesting With a Tracking Efficiency >90% Over an Ultra-Wide Source Range. 1865-1876 - Si-Yi Li, Yen-An Lin, Zheng-Lun Huang, Jia-Jyun Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A High Conversion Ratio and 97.4% High Efficiency Three-Switch Boost Converter With Duty-Dependent Charge Topology for 1.2-A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED Applications. 1877-1887 - Fangyu Mao, Yan Lu, Rui Paulo Martins:
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging. 1888-1898 - Qin Kuai, Ho-Yin Leung, Qiping Wan, Philip K. T. Mok:
A High-Efficiency Dual-Polarity Thermoelectric Energy-Harvesting Interface Circuit With Cold Startup and Fast-Searching ZCD. 1899-1912 - Ji-Young Kim, Jongsoo Lee, Ki-Ryong Kim, Sunghwan Jo, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung:
A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC. 1913-1923 - Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim:
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks. 1924-1935 - Yen-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Chieh-Pu Lo, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, Yier Jin, Meng-Fan Chang:
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device. 1936-1949
Volume 57, Number 7, July 2022
- Rabia Tugce Yazicigil, Salvatore Levantino:
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC). 1955-1956 - Jin Jin, Jianhui Wu, Rinaldo Castello, Danilo Manstretta:
A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter. 1957-1967 - Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua:
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications. 1968-1981 - Anirudh Kankuppe, Sehoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Siddhartha Sinha, Piet Wambacq, Jan Craninckx:
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS. 1982-1996 - Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx:
Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS. 1997-2010 - Dawei Mai, Yann Donnelly, Michael Peter Kennedy, Stefano Tulisi, James Breslin, Patrick Griffin, Michael Connor, Stephen Brookes, Brian Shelly, Mike Keaveney:
Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer. 2011-2023 - Thomas Bücher, Janusz Grzyb, Philipp Hillger, Holger Rücker, Bernd Heinemann, Ullrich R. Pfeiffer:
A Broadband 300 GHz Power Amplifier in a 130 nm SiGe BiCMOS Technology for Communication Applications. 2024-2034 - Huajun Zhang, Nuriel N. M. Rozsa, Marco Berkhout, Qinwen Fan:
A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band. 2035-2044 - Tzu-Hsien Yang, Yong-Hwa Wen, Chun-Kai Chiu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A Pre-Charge Tracking Technique in the 40 MHz High-Speed Switching 48-to-5 V GaN-Based DC-DC Buck Converter for Reducing Large Self-Commutation Loss and Achieving a High Efficiency of 95.4%. 2045-2053 - Xinjian Liu, Benton H. Calhoun, Shuo Li:
A Sub-nW 93% Peak Efficiency Buck Converter With Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control. 2054-2067 - Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. 2068-2077 - Hanyue Li, Yuting Shen, Haoming Xin, Eugenio Cantatore, Pieter Harpe:
A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping. 2078-2089 - Amir Bozorg, Robert Bogdan Staszewski:
A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection. 2090-2101 - Edgar Felipe Garay, David Joseph Munzer, Hua Wang:
A 150 GHz Lens-Free Large FoV Regenerative 2 × 2 Transceiver Array With 31% DC-to-EIRP Efficiency and -70 dBm Sensitivity for a 70 cm Bidirectional Peer-to-Peer Link. 2102-2113 - Sehoon Park, Dae-Woong Park, Kristof Vaesen, Anirudh Kankuppe, Siddhartha Sinha, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS. 2114-2129 - Aboozar Ghorbani-Nejad, Amir Nikpaik, Abdolreza Nabavi, Amir Hossein Masnadi Shirazi, Shahriar Mirabbasi, Sudip Shekhar:
Optimum Conditions for Efficient Second-Harmonic Power Generation in mm-Wave Harmonic Oscillators. 2130-2142 - Jingzhou Pang, Chen-Hao Chu, Jiayan Wu, Zhijiang Dai, Mingyu Li, Songbai He, Anding Zhu:
Broadband GaN MMIC Doherty Power Amplifier Using Continuous-Mode Combining for 5G Sub-6 GHz Applications. 2143-2154 - Mahmoud Mahdipour Pirbazari, Andrea Mazzanti:
E-Band Frequency Sextupler With >35 dB Harmonics Rejection Over 20 GHz Bandwidth in 55 nm BiCMOS. 2155-2166 - Zhengkun Shen, Haoyun Jiang, Fan Yang, Yixiao Wang, Zherui Zhang, Junhua Liu, Huailin Liao:
A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope. 2167-2180 - Qihui Zhang, Ning Ning, Zhong Zhang, Jing Li, Kejun Wu, Yong Chen, Qi Yu:
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration. 2181-2195 - Qi Cheng, Lin Cong, Hoi Lee:
A 48-80-V Input 2-MHz Adaptive ZVT-Assisted Bus Converter With Light-Load Efficiency Improvement. 2196-2207 - Jaehan Park, ByungJun Kim, Jae-Yoon Sim:
A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology. 2208-2219 - K. Gaurav Kumar, Baibhab Chatterjee, Shreyas Sen:
CS-Audio: A 16 pJ/b 0.1-15 Mbps Compressive Sensing IC With DWT Sparsifier for Audio-AR. 2220-2235 - Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park:
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. 2236-2249 - Xu Bai, Naoki Banno, Makoto Miyamura, Ryusuke Nebashi, Koichiro Okamoto, Hideaki Numata, Noriyuki Iguchi, Masanori Hashimoto, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada:
Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation. 2250-2262 - Yuqi Su, Hyunjoon Kim, Bongjin Kim:
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems. 2263-2273
Volume 57, Number 8, August 2022
- Pavan Kumar Hanumolu:
Guest Editorial Message From the Outgoing Editor-in-Chief. 2279 - Dennis Sylvester:
Message From the Incoming Editor-in-Chief. 2280 - Geunhaeng Lee, Junyoung Jang, Ji-Hoon Kim, Tae Wook Kim:
An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation. 2281-2291 - Ibrahim Abdo, Carrel da Gomez, Chun Wang, Kota Hatano, Qi Li, Chenxin Liu, Kiyoshi Yanagisawa, Ashbir Aviat Fadila, Takuya Fujimura, Tsuyoshi Miura, Korkut Kaan Tokgoz, Jian Pang, Hiroshi Hamada, Hideyuki Nosaka, Atsushi Shirane, Kenichi Okada:
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. 2292-2308 - Zhixian Deng, Huizhen Jenny Qian, Xun Luo:
A Reflectionless Receiver With Absorptive IF Amplifier and Dual-Path Noise-Canceling LNA. 2309-2319 - Zheng Liu, Kaushik Sengupta:
A 44-64-GHz mmWave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster Impedance Tuner. 2320-2335 - Zhiyu Chen, Wooyeol Choi, Kenneth K. O:
300-GHz Double-Balanced Up-Converter Using Asymmetric MOS Varactors in 65-nm CMOS. 2336-2347 - Zhipeng Wang, Kaixue Ma, Zonglin Ma, Haipeng Fu, Jiangtao Xu:
A 20.7-43.8-GHz Low Power Reconfigurable ×2/× 3 Frequency Multiplier for Multiple 5G-mm-Wave Bands. 2348-2361 - Zoltán Tibenszky, Mengqi Cui, Thomas Klosa, Corrado Carta, Frank Ellinger:
A Novel 61.25 GHz Monostatic CMOS Interrogator for Batteryless Backscattering RFID Solutions. 2362-2373 - Yatao Peng, Andrea Ruffino, Tsung-Yeh Yang, John Michniewicz, Miguel Fernando Gonzalez-Zalba, Edoardo Charbon:
A Cryo-CMOS Wideband Quadrature Receiver With Frequency Synthesizer for Scalable Multiplexed Readout of Silicon Spin Qubits. 2374-2389 - Hao Qiu, Takayasu Sakurai, Makoto Takamiya:
A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC. 2390-2403 - Sivaneswaran Sankar, Po-Hung Chen, Maryam Shojaei Baghini:
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation. 2404-2417 - Woojun Choi, Jan A. Angevare, Injun Park, Kofi A. A. Makinwa, Youngcheol Chae:
A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From -40 °C to 85 °C. 2418-2428 - Çagri Gürleyük, Sining Pan, Kofi A. A. Makinwa:
A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From -45 °C to 85 °C. 2429-2437 - Thije Rooijers, Johan H. Huijsing, Kofi A. A. Makinwa:
An Auto-Zero-Stabilized Voltage Buffer With a Quiet Chopping Scheme and Constant Sub-pA Input Current. 2438-2448 - Yongjae Park, Ji-Hyoung Cha, Su-Hyun Han, Jee-Ho Park, Seong-Jin Kim:
A 3.8-µW 1.5-NEF 15-GΩ Total Input Impedance Chopper Stabilized Amplifier With Auto-Calibrated Dual Positive Feedback in 110-nm CMOS. 2449-2461 - Jun-Hwan Jang, Hui-Dong Gwon, Tae-Hwang Kong, Jun-Hyeok Yang, Byong-Deok Choi:
A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS. 2462-2473 - Qi Cheng, Jin Liu, Hoi Lee:
A Wide-Input-Range Low-Profile Adaptive Delay Compensated Hysteretic LED Driver With Enhanced Current Accuracy. 2474-2485 - Li-Yang Chen, Abhinav Kumar Vinod, James F. McMillan, Hangbo Yang, Chee Wei Wong, Chih-Kong Ken Yang:
A Pulsed-Coherent Lidar With Sub-10 μm Precision. 2486-2497 - Ruilin Zhang, Xingyu Wang, Kunyang Liu, Hirofumi Shinohara:
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement. 2498-2508 - Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza, Felice Crupi:
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. 2509-2520 - Tianyu Wang, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu:
A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process. 2521-2531 - Adelson Chua, Michael I. Jordan, Rikky Muller:
SOUL: An Energy-Efficient Unsupervised Online Learning Seizure Detection Classifier. 2532-2544 - Ningyuan Cao, Baibhab Chatterjee, Jianbo Liu, Boyang Cheng, Minxiang Gong, Muya Chang, Shreyas Sen, Arijit Raychowdhury:
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller. 2545-2559 - Jinshan Yue, Yongpan Liu, Zhe Yuan, Xiaoyu Feng, Yifan He, Wenyu Sun, Zhixiao Zhang, Xin Si, Ruhui Liu, Zi Wang, Meng-Fan Chang, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang:
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. 2560-2573 - Yixiong Yang, Yongpan Liu, Zhe Yuan, Wenyu Sun, Ruoyang Liu, Jingyu Wang, Jinshan Yue, Xiaoyu Feng, Zhuqing Yuan, Xueqing Li, Huazhong Yang:
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications. 2574-2585 - Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst:
DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm. 2586-2596
Volume 57, Number 9, September 2022
- Philipp Thomas, Jakob Finkbeiner, Markus Grözing, Manfred Berroth:
Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s. 2599-2610 - Hayden Bialek, Ali Binaie, Sohail Ahasan, Kamala Raghavan Sadagopan, Matthew L. Johnston, Harish Krishnaswamy, Arun Natarajan:
A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers. 2611-2625 - Kyung-Sik Choi, Keun-Mok Kim, Dzuhri Radityo Utomo, In-Young Lee, Sang-Gug Lee:
A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL. 2626-2639 - Hossein Razavi, Behzad Razavi:
A 0.4-6 GHz Receiver for Cellular and WiFi Applications. 2640-2657 - Yanshu Guo, Zhongyuan Fang, Kai Tang, Zhaoyang Weng, Chuanshi Yang, Nan Wang, Eldwin Jiaqiang Ng, Zhihua Wang, Chun-Huat Heng, Hanjun Jiang, Yuanjin Zheng:
A 164- $\mu$ W 915-MHz Sub-Sampling Phase-Tracking Zero-IF Receiver With 5-Mb/s Data Rate for Short-Range Applications. 2658-2671 - Mohammad Barzgari, Ali Ghafari, Masoud Meghdadi, Ali Medi:
A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit. 2672-2684 - Huanbo Li, Jixin Chen, Debin Hou, Zekun Li, Rui Zhou, Zhe Chen, Pinpin Yan, Wei Hong:
W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication. 2685-2701 - Yongran Yi, Dixian Zhao, Jiajun Zhang, Peng Gu, Yuan Chai, Huiqi Liu, Xiaohu You:
A 24-29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G New Radio. 2702-2718 - Young-Seok Noh, Jeong-Il Seo, Hyun-Sik Kim, Sang-Gug Lee:
A Reconfigurable DC-DC Converter for Maximum Thermoelectric Energy Harvesting in a Battery-Powered Duty-Cycling Wireless Sensor Node. 2719-2730 - Tzu-Hsien Yang, Yong-Hwa Wen, Yu-Jheng Ouyang, Chun-Kai Chiu, Bo-Kuan Wu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A 94.3% Peak Efficiency Adaptive Switchable CCM and DCM Single-Inductor Multiple-Output Converter With 0.03 mV/mA Low Crosstalk and 185 nA Ultralow Quiescent. 2731-2740 - Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan:
A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing. 2741-2751 - Arda Uran, Kerim Türe, Cosimo Aprile, Alix Trouillet, Florian Fallegger, Emilie C. M. Revol, Azita Emami, Stéphanie P. Lacour, Catherine Dehollain, Yusuf Leblebici, Volkan Cevher:
A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. 2752-2763 - Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS. 2764-2777 - Chaegang Lim, Yohan Choi, Jaegeun Song, Soonsung Ahn, Seokwon Jang, Chulwoo Kim:
An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter. 2778-2790 - Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu:
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique. 2791-2801 - Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua:
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise. 2802-2811 - Qiyao Jiang, Quan Pan:
Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS. 2812-2828 - Suneui Park, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi:
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. 2829-2840 - Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi:
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. 2841-2855 - Guanrong Hou, Behzad Razavi:
A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance. 2856-2867 - Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu:
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References. 2868-2877 - Abhishek Jain, Andrea Mario Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin:
Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing. 2878-2890
Volume 57, Number 10, October 2022
- Jung-Hwan Choi, Po-Chiun Huang, Shouyi Yin, Woogeun Rhee:
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC). 2895-2897 - Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Jih Ren Goh, C. Thomas Gray:
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop. 2898-2908 - Jee-Ho Park, Jung-Hye Hwang, Changyong Shin, Seong-Jin Kim:
A BJT-Based Temperature-to-Frequency Converter With ± 1°C (3\Σ) Inaccuracy From - 40 °C to 140 °C for On-Chip Thermal Monitoring. 2909-2918 - Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery. 2919-2933 - Beomsoo Park, Changsok Han, Nima Maghari:
Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators. 2934-2943 - Surin Gweon, Sanghoon Kang, Kwantae Kim, Hoi-Jun Yoo:
FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems. 2944-2956 - Jongmin Lee, Minsun Kim, Minhyeok Jeong, Gicheol Shin, Yoonmyung Lee:
A 20F2/Bit Current-Integration-Based Differential nand-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security. 2957-2968 - Jeongwon Choe, Youngjoo Lee:
High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm. 2969-2978 - Zule Xu:
A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration. 2979-2987 - Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano, Naoya Toshida, Akifumi Kasamatsu, Kunio Sakakibara, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima:
A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface. 2988-2998 - Masoud Pashaeifar, Leo C. N. de Vreede, Morteza S. Alavi:
A Millimeter-Wave CMOS Series-Doherty Power Amplifier With Post-Silicon Inter-Stage Passive Validation. 2999-3013 - Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong:
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. 3014-3024 - Pen-Jui Peng, Po-Lin Lee, Hsiang-En Huang, Wei-Jian Huang, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng:
A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS. 3025-3035 - Han Wu, Miaolin Zhang, Zhichun Shao, Jiaqi Guo, Kian Ann Ng, Liwei Lin, Jerald Yoo:
An Ultrasound ASIC With Universal Energy Recycling for >7-m All-Weather Metamorphic Robotic Vision. 3036-3047 - Hyeyeon Lee, Changuk Lee, Inhee Lee, Youngcheol Chae:
A 0.033-mm2 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF. 3048-3057 - Yuming He, Federico Corradi, Chengyao Shi, Stan van der Ven, Martijn Timmermans, Jan Stuijt, Paul Detterer, Pieter Harpe, Lucas Lindeboom, Evelien Hermeling, Geert Langereis, Elisabetta Chicca, Yao-Hong Liu:
An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves. 3058-3070 - Yoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Injun Choi, Jimin Koo, Mi Kyung Kim, Hyunjoo Jenny Lee, Sohmyung Ha, Minkyu Je:
A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces. 3071-3082 - Dongsuk Kang, Jae-Woo Park, Injae Park, Minsu Park, Xuefan Jin, Kyu-Dong Hwang, Dae-Han Kwon, Jung-Hoon Chun:
A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer. 3083-3093 - Masaya Nakano, Yoshinobu Kaneda, Satoru Nakanishi, Yasumitsu Murai, Yosuke Tashiro, Yasuhiko Taito, Tomoya Ogawa, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier. 3094-3102 - Fukashi Morishita, Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Masao Ito:
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera. 3103-3113 - Liang Gao, Chi Hou Chan:
A 0.68-0.72-THz 2-D Scalable Radiator Array With -3-dBm Radiated Power and 27.3-dBm EIRP in 65-nm CMOS. 3114-3124 - Hooman Saeidi, Suresh Venkatesh, ChandraKanth Reddy Chappidi, Tushar Sharma, Chengjie Zhu, Kaushik Sengupta:
A 4 × 4 Steerable 14-dBm EIRP Array on CMOS at 0.41 THz With a 2-D Distributed Oscillator Network. 3125-3138 - Tian Guo, Woobin Kang, Jeongjin Roh:
A 0.9-μA Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive Feed-Forward Ripple Cancellation Technique. 3139-3149 - Priya Venugopal, Murali Krishna Rajendran, Gajendranath Chowdary:
A Constant-Energy-Packet-Extraction-Based MPPT Technique With 98% Average Extraction Efficiency for Wide Range Generic Ambient Energy Scavenging Supporting 1000 × Source Resistance Range. 3150-3163 - Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Tianbao Chen, Xinhan Lin, Leibo Liu, Shaojun Wei, Shouyi Yin:
Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning. 3164-3178
Volume 57, Number 11, November 2022
- Vyshnavi Suntharalingam, Fabio Sebastiano:
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). 3183-3185 - Liuhao Wu, Jiaqi Guo, Rucheng Jiang, Yande Peng, Han Wu, Jiamin Li, Yang Luo, Liwei Lin, Jerald Yoo:
An Ultrasound Imaging System With On-Chip Per-Voxel RX Beamfocusing for Real-Time Drone Applications. 3186-3199 - Seonghyeok Park, Bumjun Kim, Su-Hyun Han, Junhee Cho, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim:
An 80 × 60 Flash LiDAR Sensor With In-Pixel Delta-Intensity Quaternary Search Histogramming TDC. 3200-3211 - Changuk Lee, Byeongseol Kim, Jejung Kim, Sangwon Lee, Taejune Jeon, Woojun Choi, Sunggu Yang, Jong-Hyun Ahn, Joonsung Bae, Youngcheol Chae:
A Miniaturized Wireless Neural Implant With Body-Coupled Power Delivery and Data Transmission. 3212-3227 - Yannick M. Hopf, Boudewine W. Ossenkoppele, Mehdi Soozande, Emile Noothout, Zu-Yao Chang, Chao Chen, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs:
A Pitch-Matched Transceiver ASIC With Shared Hybrid Beamforming ADC for High-Frame-Rate 3-D Intracardiac Echocardiography. 3228-3242 - Uisub Shin, Cong Ding, Bingzhao Zhu, Yashwanth Vyza, Alix Trouillet, Emilie C. M. Revol, Stéphanie P. Lacour, Mahsa Shoaran:
NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC. 3243-3257 - Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. 3258-3273 - Kiseo Kang, Donggyu Minn, Seongun Bae, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Jae-Yoon Sim:
A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit. 3274-3287 - Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins:
A 108-nW 0.8-mm2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS. 3288-3297 - Kwantae Kim, Chang Gao, Rui Graça, Ilya Kiselev, Hoi-Jun Yoo, Tobi Delbruck, Shih-Chii Liu:
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction. 3298-3311 - Xiaohua Huang, Horacio Londoño-Ramírez, Marco Ballini, Chris Van Hoof, Jan Genoe, Sebastian Haesler, Georges G. E. Gielen, Nick Van Helleputte, Carolina Mora Lopez:
Actively Multiplexed μECoG Brain Implant System With Incremental-ΔΣ ADCs Employing Bulk-DACs. 3312-3323 - Ziyue Xu, Adam Khalifa, Ankit Mittal, Mehdi Nasrollahpourmotlaghzanjani, Diptashree Das, Marvin Onabajo, Nian Xiang Sun, Sydney S. Cash, Aatmesh Shrivastava:
A 30% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants. 3324-3335 - Kyung-Sik Choi, Keun-Mok Kim, Jinho Ko, Sang-Gug Lee:
A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration. 3336-3347 - Chung-Ching Lin, Chase Puglisi, Veljko Boljanovic, Han Yan, Erfan Ghaderi, Jayce Jeron Gaddis, Qiuyan Xu, Sreeni Poolakkal, Danijela Cabric, Subhanshu Gupta:
Multi-Mode Spatial Signal Processor With Rainbow-Like Fast Beam Training and Wideband Communications Using True-Time-Delay Arrays. 3348-3360 - Chong-Sin Huang, Tzu-Yu Tzeng, Wei-Cheng Huang, Yi-Hsiang Kao, Jie-Lin Wu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
An Energy Recycling Envelope Tracking Supply Modulator Assisted by Small Cap Replica With 89.7% Efficiency and 37% Reduced Linear Amplifier Current for 150 MHz Bandwidth 5G New Radio RF Applications. 3361-3369 - Shuxin Ming, Jinyao Yang, Jin Zhou:
A Commutated-LC RF Broadband Delay Circuit. 3370-3383 - R. S. Ashwin Kumar, Nagendra Krishnapura, Paramita Banerjee:
Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier. 3384-3395 - Si-Yi Li, Bo-Ruen Chen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
48-to-1 V Direct Conversion Using High-Voltage Storage and Low-Voltage Boost Bootstrap Technique and Early Comparison On-Time Generator for Precise Nanosecond Pulses and 90.3% Efficiency in Automotive Applications. 3396-3406 - Mohamed A. Mokhtar, Ahmed Abdelaal, Markus Sporer, Joachim Becker, John G. Kauffman, Maurits Ortmanns:
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS. 3407-3417 - Raviteja Theertham, Satya Narayana Ganta, Shanthi Pavan:
Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs. 3418-3428 - Ernest So, Pyungwoo Yeon, E. J. Chichilnisky, Amin Arbabian:
An RF-Ultrasound Relay for Adaptive Wireless Powering Across Tissue Interfaces. 3429-3441 - Cem Yalcin, Nathan Tessema Ersaro, Mohammad Meraj Ghanbari, George Bocchetti, Sina Faraji Alamouti, Nick Antipa, Daniel Lopez, Nicolas C. Pégard, Laura Waller, Rikky Muller:
A MEMS-Based Optical Scanning System for Precise, High-Speed Neural Interfacing. 3442-3452 - Shanshan Xie, Siddhartha Raman Sundara Raman, Can Ni, Meizhi Wang, Mengtian Yang, Jaydeep P. Kulkarni:
Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems. 3453-3465 - Chengshuo Yu, Taegeun Yoo, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim:
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks. 3466-3476 - Jiacong Sun, Hao Guo, Geng Li, Hailong Jiao:
An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit. 3477-3489 - Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang:
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. 3490-3502
Volume 57, Number 12, December 2022
- Dennis Sylvester:
New Associate Editor. 3507 - Dennis Sylvester:
New Associate Editor. 3508 - Wanghua Wu, Hiroyuki Ito, Jens Anders, Ahmed M. A. Ali, Gaël Pillonnet:
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). 3509-3513 - Alessandro Franceschin, Domenico Riccardi, Andrea Mazzanti:
Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance. 3514-3526 - Hangi Park, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi:
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. 3527-3537 - Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. 3538-3551 - Dihang Yang, David Murphy, Hooman Darabi, Arya Behzad, Asad A. Abidi, Stephen Au, Sraavan R. Mundlapudi, Kejian Shi, Weiyu Leng:
A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application. 3552-3566 - Xingcun Li, Wenhua Chen, Huibo Wu, Shuyang Li, Xiang Yi, Ruonan Han, Zhenghe Feng:
A 110-to-130 GHz SiGe BiCMOS Doherty Power Amplifier With a Slotline-Based Power Combiner. 3567-3581 - Steven Callender, Abhishek Agrawal, Amy Whitcombe, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Christopher D. Hull, Stefano Pellerano:
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET. 3582-3598 - Bodhisatwa Sadhu, Arun Paidimarri, Duixian Liu, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Wooram Lee, Kevin Xiaoxiong Gu, Jean-Olivier Plouchart, Christian W. Baks, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia:
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas. 3599-3616 - Yi Zhang, Jian Pang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR. 3617-3630 - Xibi Chen, Xiang Yi, Muhammad Ibrahim Wasiq Khan, Xingcun Li, Wenhua Chen, Jianfeng Zhu, Yang Yang, Kenneth E. Kolodziej, Nathan M. Monroe, Ruonan Han:
A 140-GHz FMCW TX/RX-Antenna-Sharing Transceiver With Low-Inherent-Loss Duplexing and Adaptive Self-Interference Cancellation. 3631-3645 - Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee:
A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET. 3646-3655 - Minyoung Song, Yu Huang, Hubregt J. Visser, Jac Romme, Yao-Hong Liu:
An Energy-Efficient and High-Data-Rate IR-UWB Transmitter for Intracortical Neural Sensing Interfaces. 3656-3668 - Haijun Shao, Pui-In Mak, Gengzhen Qi, Rui Paulo Martins:
A 266-μW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77-dB SFDR and -3-dBm OOB-B-1 dB. 3669-3680 - Arthur Campos de Oliveira, Sining Pan, Remco J. Wiegerink, Kofi A. A. Makinwa:
A MEMS Coriolis-Based Mass-Flow-to-Digital Converter for Low Flow Rate Sensing. 3681-3692 - Bo Wang, Man-Kay Law:
Subranging BJT-Based CMOS Temperature Sensor With a ±0.45 °C Inaccuracy (3σ) From -50 °C to 180 °C and a Resolution-FoM of 7.2 pJ·K² at 150 °C. 3693-3703 - Ippei Akita, Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu, Masakazu Hioki:
An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer. 3704-3715 - Zhong Tang, Roger Luis Brito Zamparette, Yoshikazu Furuta, Tomohiro Nezuka, Kofi A. A. Makinwa:
A Versatile ±25-A Shunt-Based Current Sensor With ±0.25% Gain Error From -40 °C to 85 °C. 3716-3725 - Shoubhik Karmakar, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan:
A -91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping. 3726-3735 - Huajun Zhang, Marco Berkhout, Kofi A. A. Makinwa, Qinwen Fan:
A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier. 3736-3745 - Corentin Pochet, Drew A. Hall:
A Pseudo-Virtual Ground Feedforwarding Technique Enabling Linearization and Higher Order Noise Shaping in VCO-Based ΔΣ Modulators. 3746-3756 - Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC. 3757-3767 - Muhammed Bolatkale, Robert Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, Bernard Burdiek, Lucien J. Breems:
A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction. 3768-3780 - Qilong Liu, Lucien J. Breems, Shagun Bajoria, Muhammed Bolatkale, Robert Rutten, Georgi I. Radulov:
A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS. 3781-3793 - Jia-Ching Wang, Tai-Haur Kuo:
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier. 3794-3803 - Tian Xie, Tzu-Han Wang, Zhe Liu, Shaolan Li:
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. 3804-3815 - Christoph Rindfleisch, Bernhard Wicht:
A 110/230 V AC and 15-400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer. 3816-3824 - Jiho Lee, Sang-Han Lee, Gyeong-Gu Kang, Jae-Hyun Kim, Gyu-Hyeong Cho, Hyun-Sik Kim:
A Triboelectric Energy-Harvesting Interface With Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Techniques. 3825-3839 - Jeong-Hyun Cho, Dong-Kyu Kim, Hong-Hyun Bae, Yong-Jin Lee, Seok-Tae Koh, Young-Hwan Choo, Ji-Seon Paek, Hyun-Sik Kim:
A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-Allocation and Fine-Grained Phase-Shedding Techniques. 3840-3852 - Zeguo Liu, Jingyi Yuan, Feng Wu, Lin Cheng:
A 12V/24V-to-1V PWM-Controlled DSD Converter With Delay-Insensitive and Dual-Phase Charging Techniques for Fast Transient Responses. 3853-3864 - Dong Yan, Dongsheng Ma:
A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC-DC Conversion. 3865-3876 - Tz-Wun Wang, Yu-Yung Kao, Sheng-Hsi Hung, Yong-Hwa Wen, Tzu-Hsien Yang, Si-Yi Li, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
Monolithic GaN-Based Driver and GaN Switch With Diode-Emulated GaN Technique for 50-MHz Operation and Sub-0.2-ns Deadtime Control. 3877-3888
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-11 21:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
