default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSIGARCH Computer Architecture News, Volume 17
Volume 17, Number 1, March 1989
- J.-P. Moskowitz, C. Jousselin:
An algebraic memory model. 55-62 - W. F. Wong:
A stack addressing scheme based on windowing. 63-69 - Pipelining through Dynamic Control ROM. 70-72
- Stanley E. Lass:
Some innovations in computer architecture. 73-77
- Philip Bitar:
Review of Parallel execution of logic programs by John Conery. Kluwer Academic Publishers 1987. 81-82
Volume 17, Number 2, April 1989
- Joel S. Emer, John L. Hennessy:
ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989. ACM Press 1989, ISBN 0-89791-300-0 [contents]
Volume 17, Number 3, June 1989
- Jean-Claude Syre:
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989. ACM 1989, ISBN 0-89791-319-1 [contents]
Volume 17, Number 4, June 1989
- André M. Van Tilborg:
Panel on future directions in parallel computer architecture. 3-53 - Neil J. Gunther, Mark T. Noga:
ParcBench: a benchmark for shared-memory architectures. 54-61 - Ali Elkateeb, Tho Le-Ngoc:
A priority strategy on RISC for real-time multitasking software applications. 62-68 - Yen-Jen Oyang:
A multiprocessor configuration in accordance with the aspects of physical and systems design. 69-73 - Heinrich Seebauer:
A memory controller executing segment operations in time 0(1). 74-81 - R. J. Schwartz:
The design and development of a dynamic program behavior measurement tool for the Intel 8086/88. 82-94 - Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus:
The first asynchronous microprocessor: the test results. 95-98 - Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, Pieter J. Hazewindus:
The design of an asynchronous microprocessor. 99-110 - F. Cornett:
The UT1000 microprogramming simulator: an educational tool. 111-118 - C. K. Yuen, W. F. Wong:
A bidirectional data driven Lisp engine for the direct execution of Lisp in parallel. 119-130
Volume 17, Number 5, September 1989
- Mark Smotherman:
A sequencing-based taxonomy of I/0 systems and review of historical machines. 5-15 - Robert Cousins:
DMA considerations on RISC workstations. 16-23 - Randy H. Katz:
A project on high performance I/0 subsystems. 24-31 - Peter C. Dibble, Michael L. Scott
:
Beyond striping: the bridge multiprocessor file system. 32-39 - A. L. Narasimha Reddy, Prithviraj Banerjee:
A study parallel disk organizations. 40-47 - Jonathan M. Smith, Gerald Q. Maguire Jr.:
Measured response times for page-sized fetches on a network. 48-54 - Barry L. Wolman, T. M. Olson:
IOBENCH: a system independent IO benchmark. 55-70 - T. M. Oslon:
Disk array performance in a random IO environment. 71-77 - Barry L. Wolman:
An analysis of server-based locking. 78-82 - Eddy H. Debaere:
Instruction-path coprocessing to solve some RISC problems. 83-94 - Heinrich Seebauer:
A memory controller executing segment operations in time 0(1). 95-102 - P. K. Chiu:
Representation of logic functions by if-then clauses. 103-107 - Cristian Baleanu, Dan Tomescu:
Embedding computers in a cellular array. 108-115 - Stanley E. Lass:
On hardware enhanced 80386 software emulation, compiled emulation, a program distribution language, and pack computers. 116-118
Volume 17, Number 6, December 1989
- Daniel Litaize, Omar Hammami, Mustapha Lalam, Abdelaziz Mzoughi, Pascal Sainrat:
Multiprocessors with a serial multiport memory and a pseudo crossbar of serial links used s a processor-memeory switch. 8-21 - Gerhard Fritsch, Wolfgang Henning, H. Hessenauer, Rainer Klar, Claus-Uwe Linster, C. W. Oehlrich, Peter Schlenk, Jens Volkert:
Distributed shared memory multiprocessor architecture MEMSY for high performance paralel computations. 22-35 - Abraham Mendelson, Dhiraj K. Pradhan, Adit D. Singh:
A single cached copy data coherence scheme for multiprocessor systems. 36-49 - Dror G. Feitelson, Larry Rudolph:
Architecture for a multi-user general-purpose parllel system. 50-56 - Donna J. Quammen, D. Richard Miller, Daniel Tabak:
Register window architecture for multitasking applications. 57-66 - Arnold L. Rosenberg:
Efficient emulations of interconnection networks. 67-79 - Isaac D. Scherson, Peter F. Corbett:
Description and performance of a class of orthogonal multiprocessor networks. 80-90 - Llana David, Ran Ginosar, Michael Yoeli:
An efficient implementation of Boolean functions nd finite state machine as self-timed circuit. 91-104 - Apostolos Dollan, Robert F. Krick:
The case for the sustained performance computer architecture. 129-136 - Eric E. Johnson:
Working set prefetching for cache memories. 137-141 - K.-H. Lee, C. H. Lam:
Massage-passing controllerr for a shared-memory multiprocessor. 142-149 - Tsong-Chih Hsu, Ling-Yang Kung:
Logic and conflict-free vector addresses. 150-153 - Tsong-Chih Hsu, Ling-Yang Kung:
An address gneration unit for array accessing. 154-160 - Tsong-Chih Hsu, Ling-Yang Kung:
A hardware mechanism for priority queue. 162-169
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-27 21:27 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
