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2020 – today
- 2024
[c83]Xuan-Jun Chen, Han-Ping Chen, Chia-Lin Yang:
PointCIM: A Computing-in-Memory Architecture for Accelerating Deep Point Cloud Analytics. MICRO 2024: 1309-1322- 2023
- [j32]Chia-Lin Yang
:
Understanding Computer Architecture Sustainability. Computer 56(9): 4-5 (2023) - [j31]Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Hussam Amrouch, Chia-Lin Yang:
Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing Machine With In-Situ Synapse Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4380-4393 (2023) - [c82]Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng:
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES 2023: 11-20 - [c81]Xuan-Jun Chen, Cynthia Kuan, Chia-Lin Yang:
Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical Isometry. DAC 2023: 1-6 - [c80]Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang:
Tensor Movement Orchestration in Multi-GPU Training Systems. HPCA 2023: 1140-1152 - [c79]Mikail Yayla, Simon Thomann, Md. Mazharul Islam, Ming-Liang Wei, Shu-Yin Ho, Ahmedullah Aziz, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch:
Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories. VTS 2023: 1-10 - [i3]Mikail Yayla, Simon Thomann, Ming-Liang Wei, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch:
HW/SW Codesign for Robust and Efficient Binarized SNNs by Capacitor Minimization. CoRR abs/2309.02111 (2023) - 2022
- [j30]Chia-Lin Yang:
A Forward Speculative Interference Attack. Computer 55(6): 4-5 (2022) - [j29]Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien:
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. ACM Trans. Embed. Comput. Syst. 21(3): 24:1-24:29 (2022) - [c78]Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang:
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. ASP-DAC 2022: 122-127 - [c77]Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai:
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. ASP-DAC 2022: 702-707 - [c76]Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo:
Efficient Bad Block Management with Cluster Similarity. HPCA 2022: 503-513 - [c75]Xuan Sun, Hu Wan, Qiao Li, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue:
RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference. HPCA 2022: 1056-1070 - [c74]Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li:
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. NVMSA 2022: 1-7 - 2021
- [j28]Jun-Liang Lin, Tsung-Ting Hsieh, Yi-An Tung, Xuan-Jun Chen, Yu-Chun Hsiao, Chia-Lin Yang, Tyng-Luh Liu, Chien-Yu Chen:
ezGeno: an automatic model selection package for genomic data analysis. Bioinform. 38(1): 30-37 (2021) - [c73]Hu Wan, Xuan Sun, Yufei Cui, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue:
FlashEmbedding: storing embedding tables in SSD for large-scale recommender systems. APSys 2021: 9-16 - [c72]Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo:
Future Computing Platform Design: A Cross-Layer Design Approach. DATE 2021: 312-317 - [c71]Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Chia-Lin Yang, Hussam Amrouch:
Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization. ICCAD 2021: 1-9 - [c70]Ming-Liang Wei, Hussam Amrouch, Cheng-Lin Sung, Hang-Ting Lue, Chia-Lin Yang, Keh-Chung Wang, Chih-Yuan Lu:
Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses. IRPS 2021: 1-8 - [c69]Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien:
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads. ISCAS 2021: 1-5 - [c68]Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang:
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. ISPASS 2021: 276-287 - [i2]Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien:
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads. CoRR abs/2111.12885 (2021) - 2020
- [c67]Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li:
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. DAC 2020: 1-6
2010 – 2019
- 2019
- [c66]Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang:
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. ICCAD 2019: 1-6 - [c65]Chien-I Lee, Meng-Yao Lin, Chia-Lin Yang, Yen-Kuang Chen:
Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge Devices. ICIP 2019: 170-174 - [c64]Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li:
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. ISCA 2019: 236-249 - [c63]Cheng Ji, Lun Wang, Qiao Li, Congming Gao, Liang Shi, Chia-Lin Yang, Chun Jason Xue:
Fair Down to the Device: A GC-Aware Fair Scheduler for SSD. NVMSA 2019: 1-6 - 2018
- [c62]Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang:
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. DAC 2018: 112:1-112:6 - [c61]Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang:
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. ICCAD 2018: 31 - [i1]Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang:
LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling. CoRR abs/1810.04509 (2018) - 2017
- [j27]Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang:
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. 16(2): 127-131 (2017) - [j26]David Garrett, Chia-Lin Yang:
Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED). IEEE Des. Test 34(6): 121-122 (2017) - [j25]Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang:
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives. IEEE Trans. Computers 66(8): 1457-1463 (2017) - [j24]Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration. ACM Trans. Design Autom. Electr. Syst. 22(2): 27:1-27:22 (2017) - [c60]Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang:
Enabling fast preemption via Dual-Kernel support on GPUs. ASP-DAC 2017: 121-126 - [c59]Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang:
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach. DAC 2017: 5:1-5:6 - [c58]David Garrett, Chia-Lin Yang:
Message from the general co-chairs. ISLPED 2017: 1 - [c57]Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung:
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS 2017: 127-128 - 2016
- [j23]Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li:
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality. IEEE Trans. Computers 65(4): 1090-1102 (2016) - [c56]Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li:
MCSSim: A memory channel storage simulator. ASP-DAC 2016: 153-158 - [c55]Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang:
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. DAC 2016: 5:1-5:6 - 2015
- [j22]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ACM Trans. Archit. Code Optim. 12(2): 19:19:1-19:19:24 (2015) - [j21]Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang:
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach. ACM Trans. Embed. Comput. Syst. 14(1): 8:1-8:26 (2015) - [c54]Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li:
Fine-grained write scheduling for PCM performance improvement under write power budget. ISLPED 2015: 19-24 - [c53]Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang:
Improving DRAM latency with dynamic asymmetric subarray. MICRO 2015: 255-266 - [c52]Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. NVMSA 2015: 1-6 - [c51]Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu:
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. RACS 2015: 430-436 - 2014
- [j20]Martin Dimitrov, Yung-Hsiang Lu, Chia-Lin Yang:
Guest Editors' Introduction: Cloud Computing for Embedded Systems. IEEE Des. Test 31(3): 6-7 (2014) - [c50]Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-Yuan Michael Wang:
NVM duet: unified working memory and persistent store architecture. ASPLOS 2014: 455-470 - [c49]Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li:
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. DAC 2014: 145:1-145:6 - [c48]Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky:
Full system simulation framework for integrated CPU/GPU architecture. VLSI-DAT 2014: 1-4 - 2013
- [c47]Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen:
DuraCache: a durable SSD cache using MLC NAND flash. DAC 2013: 166:1-166:6 - [c46]Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu:
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ISLPED 2013: 304 - [c45]Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang:
Thermal coupling aware task migration using neighboring core search for many-core systems. VLSI-DAT 2013: 1-4 - 2012
- [c44]Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang:
Memory access aware power gating for MPSoCs. ASP-DAC 2012: 121-126 - [c43]Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang:
Age-based PCM wear leveling with nearly zero search cost. DAC 2012: 453-458 - [c42]Ren-Shuo Liu, Chia-Lin Yang, Wei Wu:
Optimizing NAND flash-based SSDs via retention relaxation. FAST 2012: 11 - [c41]Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen:
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. ICCAD 2012: 458-465 - [c40]Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang:
SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD 2012: 67-74 - [c39]Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng:
A cycle-level SIMT-GPU simulation framework. ISPASS 2012: 114-115 - 2011
- [j19]James C. Chen, Kou-Huang Chen, Chien-Hsin Lin, Chia-Wen Chen, Chia-Lin Yang:
A Study of a Heuristic Capacity Planning Algorithm for Weapon Production System. Int. J. Electron. Bus. Manag. 9(1): 46-57 (2011) - [j18]Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng:
Power gating strategies on GPUs. ACM Trans. Archit. Code Optim. 8(3): 13:1-13:25 (2011) - [j17]Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen:
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems. IEEE Trans. Computers 60(6): 767-782 (2011) - [j16]Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang:
Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1293-1306 (2011) - [c38]Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang:
A SAT-based routing algorithm for cross-referencing biochips. SLIP 2011: 1-7 - 2010
- [c37]Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang:
PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE 2010: 1590-1595 - [c36]Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang:
Hierarchical memory scheduling for multimedia MPSoCs. ICCAD 2010: 190-196 - [c35]Ren-Shuo Liu, Yun-Cheng Tsai, Chia-Lin Yang:
Parallelization and characterization of GARCH option pricing on GPUs. IISWC 2010: 1-10 - [c34]Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang:
Dynamic thermal management for networked embedded systems under harsh ambient temperature variation. ISLPED 2010: 289-294 - [c33]Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang:
Memory Latency Reduction via Thread Throttling. MICRO 2010: 53-64
2000 – 2009
- 2009
- [j15]Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng:
A Predictive Shutdown Technique for GPU Shader Processors. IEEE Comput. Archit. Lett. 8(1): 9-12 (2009) - [j14]Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang:
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design. J. Syst. Archit. 55(5-6): 299-309 (2009) - [j13]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1295-1306 (2009) - [j12]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
T-trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Design Autom. Electr. Syst. 14(4): 51:1-51:28 (2009) - [j11]Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin:
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 14(4): 52:1-52:26 (2009) - [j10]Sung-Wen Wang, Shu-Sian Yang, Hong-Ming Chen, Chia-Lin Yang, Ja-Ling Wu:
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters. J. Signal Process. Syst. 57(2): 195-211 (2009) - [c32]Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu:
Thermal modeling for 3D-ICs with integrated microchannel cooling. ICCAD 2009: 256-263 - [c31]Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King:
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. ISLPED 2009: 93-98 - 2008
- [j9]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 643-653 (2008) - [j8]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1928-1941 (2008) - [j7]Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng:
Energy-Aware Flash Memory Management in Virtual Memory System. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 952-964 (2008) - [c30]Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289 - 2007
- [j6]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation. ACM J. Emerg. Technol. Comput. Syst. 3(3): 13 (2007) - [j5]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the three-dimensional transitive closure subGraph. ACM Trans. Design Autom. Electr. Syst. 12(4): 37 (2007) - [c29]Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen:
Cache leakage control mechanism for hard real-time systems. CASES 2007: 248-256 - [c28]Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King:
Energy-efficient real-time task scheduling with task rejection. DATE 2007: 1629-1634 - [c27]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. ICCAD 2007: 752-757 - [c26]Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen:
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. ICME 2007: 9 - [c25]Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. ISLPED 2007: 92-97 - [c24]Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
Efficient obstacle-avoiding rectilinear steiner tree construction. ISPD 2007: 127-134 - [c23]Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su:
An architectural co-synthesis algorithm for energy-aware network-on-chip design. SAC 2007: 680-684 - 2006
- [c22]Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen:
Branch Behavior Characterization for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference 2006: 523-530 - [c21]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Placement of digital microfluidic biochips using the t-tree formulation. DAC 2006: 931-934 - [c20]Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King:
Hierarchical value cache encoding for off-chip data bus. ISLPED 2006: 143-146 - [c19]Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang:
An energy-efficient virtual memory system with flash memory as the secondary storage. ISLPED 2006: 418-423 - [c18]Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang:
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation. ISORC 2006: 64-71 - 2005
- [j4]Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu:
Software-Controlled Cache Architecture for Energy Efficiency. IEEE Trans. Circuits Syst. Video Technol. 15(5): 634-644 (2005) - [c17]Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung:
Cache Leakage Management for Multi-programming Workloads. Asia-Pacific Computer Systems Architecture Conference 2005: 736-749 - [c16]Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang:
Joint exploration of architectural and physical design spaces with thermal consideration. ISLPED 2005: 123-126 - [c15]Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen:
Reconfigurable Platform for Content Science Research. RTCSA 2005: 481-486 - 2004
- [j3]Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee:
Tolerating memory latency through push prefetching for pointer-intensive applications. ACM Trans. Archit. Code Optim. 1(4): 445-475 (2004) - [j2]Yen-Jen Chang, Feipei Lai, Chia-Lin Yang:
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. IEEE Trans. Very Large Scale Integr. Syst. 12(8): 827-836 (2004) - [c14]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen:
Temporal floorplanning using 3D-subTCG. ASP-DAC 2004: 725-730 - [c13]Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang:
Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism. CODES+ISSS 2004: 134-139 - [c12]Yen-Jen Chang, Chia-Lin Yang, Feipei Lai:
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. DATE 2004: 16-21 - [c11]Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo:
Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. ECRTS 2004: 101-108 - [c10]Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
Temporal floorplanning using the T-tree formulation. ICCAD 2004: 300-305 - [c9]Chia-Lin Yang, Chien-Hao Lee:
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. ISLPED 2004: 114-119 - [c8]Tse-Tsung Shih, Chia-Lin Yang, Yi-Shin Tung:
Workload Characterization of the H.264/AVC Decoder. PCM (2) 2004: 957-966 - [c7]Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang:
Profit-driven uniprocessor scheduling with energy and timing constraints. SAC 2004: 834-840 - 2003
- [c6]Yen-Jen Chang, Chia-Lin Yang, Feipei Lai:
A power-aware SWDR cell for reducing cache write power. ISLPED 2003: 14-17 - 2002
- [c5]Chia-Lin Yang, Alvin R. Lebeck:
A Programmable Memory Hierarchy for Prefetching Linked Data Structures. ISHPC 2002: 160-174 - [c4]Wan-Chun Ma, Chia-Lin Yang:
Using Intel Streaming SIMD Extensions for 3D Geometry Processing. IEEE Pacific Rim Conference on Multimedia 2002: 1080-1087 - 2000
- [j1]Chia-Lin Yang, Barton Sano, Alvin R. Lebeck:
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. IEEE Trans. Computers 49(9): 934-946 (2000) - [c3]Chia-Lin Yang, Alvin R. Lebeck:
Push vs. pull: data movement for linked data structures. ICS 2000: 176-186
1990 – 1999
- 1999
- [c2]Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi:
Annotated Memory References: A Mechanism for Informed Cache Management. Euro-Par 1999: 1251-1254 - 1998
- [c1]Chia-Lin Yang, Barton Sano, Alvin R. Lebeck:
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. MICRO 1998: 14-24
Coauthor Index
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-11 21:38 CET by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
