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ORCIDShijie Zhou 0001
Person information
- affiliation: Microsoft Corporation, Redmond, USA
- affiliation (PhD 2018): University of Southern California, Los Angeles, CA, USA
Other persons with the same name
- Shijie Zhou (aka: Zhou Shijie) — disambiguation page
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2020 – today
- 2020
[j4]Shijie Zhou, Rajgopal Kannan, Viktor K. Prasanna
:
Accelerating Stochastic Gradient Descent Based Matrix Factorization on FPGA. IEEE Trans. Parallel Distributed Syst. 31(8): 1897-1911 (2020)
2010 – 2019
- 2019
- [j3]Shijie Zhou, Rajgopal Kannan, Viktor K. Prasanna, Guna Seetharaman, Qing Wu:
HitGraph: High-throughput Graph Processing Framework on FPGA. IEEE Trans. Parallel Distributed Syst. 30(10): 2249-2264 (2019) - 2018
- [c24]Shijie Zhou, Rajgopal Kannan, Hanqing Zeng, Viktor K. Prasanna:
An FPGA framework for edge-centric graph processing. CF 2018: 69-77 - [c23]Shijie Zhou, Rajgopal Kannan, Yu Min, Viktor K. Prasanna:
FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering. FPGA 2018: 259-268 - 2017
- [c22]Oded Green, James Fox, Euna Kim, Federico Busato, Nicola Bombieri, Kartik Lakhotia, Shijie Zhou, Shreyas G. Singapura, Hanqing Zeng, Rajgopal Kannan, Viktor K. Prasanna, David A. Bader:
Quickly finding a truss in a haystack. HPEC 2017: 1-7 - [c21]Shijie Zhou, Kartik Lakhotia, Shreyas G. Singapura, Hanqing Zeng, Rajgopal Kannan, Viktor K. Prasanna, James Fox, Euna Kim, Oded Green, David A. Bader:
Design and implementation of parallel PageRank on multicore platforms. HPEC 2017: 1-6 - [c20]Shijie Zhou, Rajgopal Kannan, Viktor K. Prasanna:
Accelerating low rank matrix completion on FPGA. ReConFig 2017: 1-7 - [c19]Shijie Zhou, Viktor K. Prasanna:
Accelerating Graph Analytics on CPU-FPGA Heterogeneous Platform. SBAC-PAD 2017: 137-144 - [c18]Zhe Fu, Shijie Zhou, Jun Li:
bitFA: A Novel Data Structure for Fast and Update-friendly Regular Expression Matching. SIGCOMM Posters and Demos 2017: 130-132 - 2016
- [c17]Shijie Zhou, Charalampos Chelmis, Viktor K. Prasanna:
High-Throughput and Energy-Efficient Graph Processing on FPGA. FCCM 2016: 103-110 - 2015
- [j2]Yun Rock Qu, Shijie Zhou, Viktor K. Prasanna:
A Decomposition-Based Approach for Scalable Many-Field Packet Classification on Multi-core Processors. Int. J. Parallel Program. 43(6): 965-987 (2015) - [c16]Yun Rock Qu, Hao H. Zhang, Shijie Zhou, Viktor K. Prasanna:
Optimizing Many-field Packet Classification on FPGA, Multi-core General Purpose Processor, and GPU. ANCS 2015: 87-98 - [c15]Shijie Zhou, Yun Rock Qu, Viktor K. Prasanna:
Large-scale packet classification on FPGA. ASAP 2015: 226-233 - [c14]Shijie Zhou, Viktor K. Prasanna:
Scalable GPU-Accelerated IPv6 Lookup Using Hierarchical Perfect Hashing. GLOBECOM 2015: 1-6 - [c13]Da Tong, Shijie Zhou, Viktor K. Prasanna:
High-Throughput Online Hash Table on FPGA. IPDPS Workshops 2015: 105-112 - [c12]Shijie Zhou, Charalampos Chelmis, Viktor K. Prasanna:
Accelerating Large-Scale Single-Source Shortest Path on FPGA. IPDPS Workshops 2015: 129-136 - [c11]Shijie Zhou, Charalampos Chelmis, Viktor K. Prasanna:
Optimizing memory performance for FPGA implementation of pagerank. ReConFig 2015: 1-6 - [r1]Yun Rock Qu, Shijie Zhou, Viktor K. Prasanna:
Packet Classification on Multi-core Platforms. Handbook on Data Centers 2015: 425-447 - 2014
- [j1]Shijie Zhou, Yun Rock Qu, Viktor K. Prasanna:
Multi-core implementation of decomposition-based packet classification algorithms. J. Supercomput. 69(1): 34-42 (2014) - [c10]Sanmukh R. Kuppannagari, Ren Chen, Andrea Sanny, Shreyas G. Singapura, Geoffrey Phi C. Tran, Shijie Zhou, Yusong Hu, Stephen P. Crago, Viktor K. Prasanna:
Energy performance of FPGAs on PERFECT suite kernels. HPEC 2014: 1-6 - [c9]Shijie Zhou, Shreyas G. Singapura, Viktor K. Prasanna:
High-performance packet classification on GPU. HPEC 2014: 1-6 - [c8]Yun Rock Qu, Shijie Zhou, Viktor K. Prasanna:
Performance modeling and optimizations for decomposition-based large-scale packet classification on multi-core processors. HPSR 2014: 154-161 - [c7]Shijie Zhou, Weirong Jiang, Viktor K. Prasanna:
A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms. IPCCC 2014: 1-8 - [c6]Shijie Zhou, Sihan Zhao, Viktor K. Prasanna:
400 Gbps energy-efficient multi-field packet classification on FPGA. ReConFig 2014: 1-6 - [c5]Shijie Zhou, Prashant Rao Nittoor, Viktor K. Prasanna:
High-Performance Traffic Classification on GPU. SBAC-PAD 2014: 97-104 - [c4]Shijie Zhou, Weirong Jiang, Viktor K. Prasanna:
A programmable and scalable openflow switch using heterogeneous soc platforms. HotSDN 2014: 239-240 - 2013
- [c3]Yun Rock Qu, Shijie Zhou, Viktor K. Prasanna:
High-performance architecture for dynamically updatable packet classification on FPGA. ANCS 2013: 125-136 - [c2]Shijie Zhou, Yun Rock Qu, Viktor K. Prasanna:
Multi-core Implementation of Decomposition-Based Packet Classification Algorithms. PaCT 2013: 105-119 - [c1]Yun Qu, Shijie Zhou, Viktor K. Prasanna:
Scalable Many-Field Packet Classification on Multi-core Processors. SBAC-PAD 2013: 33-40
Coauthor Index
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