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ORCIDDaisuke Kanemoto
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2020 – today
- 2024
[j16]Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
Programmable Differential Bandgap Reference Circuit for Ultra-Low-Power CMOS LSIs. IEICE Trans. Electron. 107(10): 392-399 (2024)- [j15]Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
Sub-60-mV Charge Pump and its Driver Circuit for Extremely Low-Voltage Thermoelectric Energy Harvesting. IEICE Trans. Electron. 107(10): 400-407 (2024) - [c17]Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose:
Utilizing Previously Acquired BSBL Algorithm Parameters in the Compressed Sensing Framework for EEG Measurements. ICCE 2024: 1-4 - [c16]Ryota Tsunaga, Daisuke Kanemoto, Tetsuya Hirose:
Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing. ICCE 2024: 1-5 - [c15]Riku Matsubara, Daisuke Kanemoto, Tetsuya Hirose:
Reducing Power Consumption in LNA by Utilizing EEG Signals as Basis Matrix in Compressed Sensing. ISCAS 2024: 1-5 - 2023
- [c14]Hikaru Sebe, Tomohisa Okumura, Shintaro Sumi, Daisuke Kanemoto, Po-Hung Chen, Tetsuya Hirose:
Sub-30-mV-Supply, Fully Integrated Ring Oscillator Consisting of Recursive Stacking Body-Bias Inverters for Extremely Low-Voltage Energy Harvesting. ESSCIRC 2023: 325-328 - [c13]Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices. ISCAS 2023: 1-5 - [c12]Daisuke Kanemoto, Tetsuya Hirose:
EEG Measurements with Compressed Sensing Utilizing EEG Signals as the Basis Matrix. ISCAS 2023: 1-5 - [c11]Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose:
Random Undersampling Wireless EEG Measurement Device using a Small TEG. ISCAS 2023: 1-5 - 2022
- [j14]Yuuki Harada, Daisuke Kanemoto, Takahiro Inoue, Osamu Maida, Tetsuya Hirose:
Image Quality Improvement for Capsule Endoscopy Based on Compressed Sensing with K-SVD Dictionary Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(4): 743-747 (2022) - [j13]Yuki Okabe, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose:
Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(10): 1429-1433 (2022) - [c10]Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose:
Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting. ISCAS 2022: 2773-2777 - 2021
- [j12]Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs. IEICE Electron. Express 18(6): 20210065 (2021) - [j11]Kotaro Nagai, Daisuke Kanemoto, Makoto Ohki:
Applying K-SVD Dictionary Learning for EEG Compressed Sensing Framework with Outlier Detection and Independent Component Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(9): 1375-1378 (2021) - 2020
- [j10]Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems. IEICE Electron. Express 17(11): 20200103 (2020) - [j9]Daisuke Kanemoto, Shun Katsumata, Masao Aihara, Makoto Ohki:
Compressed Sensing Framework Applying Independent Component Analysis after Undersampling for Reconstructing Electroencephalogram Signals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1647-1654 (2020) - [c9]Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting. NEWCAS 2020: 38-41
2010 – 2019
- 2019
- [c8]Shun Katsumata, Daisuke Kanemoto, Makoto Ohki:
Applying Outlier Detection and Independent Component Analysis for Compressed Sensing EEG Measurement Framework. BioCAS 2019: 1-4 - [c7]Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose:
Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter. ICECS 2019: 530-533 - 2018
- [c6]Daisuke Kanemoto, Shun Katsumata, Masao Aihara, Makoto Ohki:
Framework of Applying Independent Component Analysis After Compressed Sensing for Electroencephalogram Signals. BioCAS 2018: 1-4 - 2015
- [c5]Daisuke Kanemoto, Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya:
A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications. ASP-DAC 2015: 34-35 - [c4]Osamu Muta, Daisuke Kanemoto, Syota Fukushige, Hiroshi Furukawa:
Effect of Linearity Enhancement in A/D Conversion for Single Carrier Transmission Systems. VTC Spring 2015: 1-5 - 2014
- [j8]Toru Okazaki, Daisuke Kanemoto, Ramesh K. Pokharel, Keiji Yoshida, Haruichi Kanaya:
A design methodology for SAR ADC optimal redundancy bit. IEICE Electron. Express 11(10): 20140218 (2014) - [c3]Takahide Sato, Takeshi Nagata, Daisuke Kanemoto:
High frequency ring oscillator using capacitor based level shift circuits. APCCAS 2014: 149-152 - 2013
- [j7]Yuki Yamashita, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, Keiji Yoshida:
A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system. IEICE Electron. Express 10(8): 20130174 (2013) - 2012
- [j6]Kazuya Hokazono, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel
, Keiji Yoshida:
A novel high-precision DAC utilizing tribonacci series. IEICE Electron. Express 9(6): 515-521 (2012) - [j5]Daisuke Kanemoto, Yu Tamura, Indika U. K. Bogoda Appuhamylage, Toshimasa Matsuoka, Kenji Taniguchi:
A novel RC time constant tuning technique utilizing programmable current sources for continuous-time delta-sigma modulators. IEICE Electron. Express 9(6): 572-579 (2012) - [j4]Daisuke Kanemoto, Toru Ido, Kenji Taniguchi:
A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators. IEICE Trans. Electron. 95-C(8): 1427-1433 (2012) - [c2]Keigo Oshiro, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, Keiji Yoshida:
A small die area and high linearity 10-bit capacitive three-level DAC. APCCAS 2012: 164-167 - 2011
- [j3]Indika U. K. Bogoda Appuhamylage, Daisuke Kanemoto, Kenji Taniguchi:
A Novel 100ppm/°C current reference for ultra-low-power subthreshold applications. IEICE Electron. Express 8(3): 168-174 (2011) - [j2]Ghazal A. Fahmy, Daisuke Kanemoto, Haruichi Kanaya, Keiji Yoshida, Ramesh K. Pokharel, Awinash Anand:
A third order delta-sigma modulator employing shared opamp technique for WCDMA on 0.18um CMOS. IEICE Electron. Express 8(15): 1204-1209 (2011) - [c1]Daisuke Kanemoto, Toru Ido, Kenji Taniguchi:
A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique. ISOCC 2011: 66-69
2000 – 2009
- 2008
- [j1]Daisuke Kanemoto, Toru Ido, Kenji Taniguchi:
A novel third order Delta Sigma Modulator with one opamp shared among three integrator stages. IEICE Electron. Express 5(24): 1088-1092 (2008)
Coauthor Index
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