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Seuk Son

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affiliation: Seoul National University, Gwanak-gu, South Korea

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2020 – today

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2021
[j5]
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Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, Jaeha Kim:
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2876-2889 (2021)

2010 – 2019

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2019
[j4]
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Seuk Son, Sigang Ryu, Hwanseok Yeo, Jaeha Kim:
A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery. IEEE J. Solid State Circuits 54(10): 2823-2832 (2019)
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Sigang Ryu, Seuk Son, Jaeha Kim:
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1245-1257 (2019)
2018
[c5]
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Seuk Son, Hwanseok Yeo, Sigang Ryu, Jaeha Kim:
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery. A-SSCC 2018: 201-204
2016
[c4]
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Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son, Jaeha Kim:
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications. ISSCC 2016: 238-239
2014
[j2]
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Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim:
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function. IEEE J. Solid State Circuits 49(8): 1773-1784 (2014)
2013
[j1]
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Seuk Son, Hanseok Kim, Myeong-Jae Park, Kyung-Hoon Kim, E-Hung Chen, Brian S. Leibowitz, Jaeha Kim:
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm. IEEE J. Solid State Circuits 48(11): 2693-2704 (2013)
[c3]
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Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim:
A 9.2-GHz digital phase-locked loop with peaking-free transfer function. CICC 2013: 1-4
2012
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Myeong-Jae Park, Hanseok Kim, Seuk Son, Jaeha Kim:
A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection. CICC 2012: 1-4
[c1]
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Jihyun Ryoo, Seuk Son, Jaeha Kim:
Design of low-power high-radix switch fabric with partially-activated input and output lines. ISOCC 2012: 227-230

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