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2020 – today
- 2024
[c22]Jeongyoon Wie
, Sangwoo Jung, Taeryoung Seol, Geunha Kim, Sehwan Lee, Homin Jang, Samhwan Kim, Yeonjae Shin, Jae Eun Jang, Jaeha Kung, Arup K. George, Junghyup Lee:
A 3.3-to-11V-Supply-Range 10μW/Ch Arbitrary-Waveform-Capable Neural Stimulator with Output-Adaptive-Self-Bias and Supply-Tracking Schemes in 0.18μm Standard CMOS. CICC 2024: 1-2- [c21]Taeryoung Seol, Geunha Kim, Sehwan Lee, Samhwan Kim, Dongwook Kim, Jeongyoon Wie, Yeonjae Shin, Hongki Kang, Jae Eun Jang, Arup K. George, Junghyup Lee:
33.11 A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR 173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent Acquisition. ISSCC 2024: 562-564 - [c20]Sehwan Lee, Taeryoung Seol, Geunha Kim, Minyoung Song, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee:
A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c19]Taeryoung Seol, Sehwan Lee, Geunha Kim, Samhwan Kim, Euiseong Kim, Seungyeob Baik, Jaeha Kung, Ji-Woong Choi, Arup K. George, Junghyup Lee:
A 1V 136.6dB-DR 4kHz-BW $\Delta\Sigma$ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18\mu\mathrm{m}$ CMOS. ISSCC 2023: 482-483 - [c18]Geunha Kim, Sehwan Lee, Taeryoung Seol, Seungyeob Baik, Yeonjae Shin, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee:
A 1V-Supply $1.85\mathrm{V}_{\text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2nd-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS. ISSCC 2023: 484-485 - 2022
- [c17]Sehwan Lee, Yoonsung Choi, Geunha Kim, Seungyeob Baik, Taeryoung Seol, Homin Jang, Doyoung Lee, Minkyu Je, Ji-Woong Choi, Arup K. George, Junghyup Lee:
A 0.7V 17fJ/Step-FOMW 178.1dB-FOMSNDR 10kHz-BW 560mVPP True-ExG Biopotential Acquisition System with Parasitic-Insensitive 421MΩ Input Impedance in 0.18μm CMOS. ISSCC 2022: 336-338 - [c16]Seungyeob Baik, Taeryoung Seol, Sehwan Lee, Geunha Kim, SeongHwan Cho, Arup K. George, Junghyup Lee:
A 2.54μJ∙ppm2-FOMS Supply- and Temperature-Independent Time-Locked ΔΣ Capacitance-to-Digital Converter in 0.18-μm CMOS. VLSI Technology and Circuits 2022: 114-115 - 2021
- [c15]Jun-Woo Jang, Sehwan Lee, Dongyoung Kim, Hyunsun Park, Ali Shafiee Ardestani, Yeongjae Choi, Channoh Kim, Yoojin Kim, Hyeongseok Yu, Hamzah Abdel-Aziz, Jun-Seok Park, Heonsoo Lee, Dongwoo Lee, Myeong Woo Kim, Hanwoong Jung, Heewoo Nam, Dongguen Lim, Seungwon Lee, Joon-Ho Song, Suknam Kwon, Joseph Hassoun, Sukhwan Lim, Changkyu Choi:
Sparsity-Aware and Re-configurable NPU Architecture for Samsung Flagship Mobile SoC. ISCA 2021: 15-28 - [c14]Jun-Seok Park, Jun-Woo Jang, Heonsoo Lee, Dongwoo Lee, Sehwan Lee, Hanwoong Jung, Seungwon Lee, Suknam Kwon, Kyung-Ah Jeong, Joon-Ho Song, Sukhwan Lim, Inyup Kang:
9.5 A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC. ISSCC 2021: 152-154 - 2020
- [j3]Soonyoung Hong, Sehwan Lee, Junghyup Lee, Minkyu Je:
A Multi-Mode ULP Receiver Based on an Injection-Locked Oscillator for IoT Applications. IEEE Access 8: 76966-76979 (2020) - [j2]Pramod P. Udupa, Gopinath Mahale, Kiran Kolar Chandrasekharan, Sehwan Lee:
IKW: Inter-Kernel Weights for Power Efficient Edge Computing. IEEE Access 8: 90450-90464 (2020) - [j1]Gopinath Mahale, Pramod P. Udupa, Kiran Kolar Chandrasekharan, Sehwan Lee:
WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 4278-4289 (2020) - [c13]Saptarsi Das, Arnab Roy, Kiran Kolar Chandrasekharan, Ankur Deshwal, Sehwan Lee:
A Systolic Dataflow Based Accelerator for CNNs. ISCAS 2020: 1-5 - [c12]Pramod P. Udupa, Gopinath Mahale, Kiran Kolar Chandrasekharan, Sehwan Lee:
Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c11]Jinook Song, Yunkyo Cho, Jun-Seok Park, Jun-Woo Jang, Sehwan Lee, Joon-Ho Song, Jae-Gon Lee, Inyup Kang:
An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC. ISSCC 2019: 130-132 - 2018
- [c10]Taeryoung Seol, Sehwan Lee, Junghyup Lee:
A Wearable Electrocardiogram Monitoring System Robust to Motion Artifacts. ISOCC 2018: 241-242 - [c9]Sehwan Lee, Arup K. George, Taeju Lee, Jun-Uk Chu, Sungmin Han, Ji-Hoon Kim, Minkyu Je, Junghyup Lee:
A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS. ISSCC 2018: 472-474 - 2017
- [c8]Sehwan Lee, Ju-Hwan Lee:
Does Spatial Attribute between 2D and 3D Virtual Spaces make Different User Immersion of Audio-Visual Events? ICCAE 2017: 56-59 - 2011
- [c7]Sehwan Lee, Bitna Lee, Kern Koh, Hyokyung Bahn:
A Demand-Based FTL Scheme Using Dualistic Approach on Data Blocks and Translation Blocks. RTCSA (1) 2011: 167-176 - [c6]Sehwan Lee, Bitna Lee, Kern Koh, Hyokyung Bahn:
A lifespan-aware reliability scheme for RAID-based flash storage. SAC 2011: 374-379 - 2010
- [c5]Sehwan Lee, Kern Koh, Hyokyung Bahn:
Unifying Buffer Replacement and Prefetching with Data Migration for Heterogeneous Storage Devices. ICPADS 2010: 330-337
2000 – 2009
- 2009
- [c4]Sehwan Lee, Seunghwan Hyun, Kern Koh:
Selective Context Switching on Flash Memory. ICCSA Workshops 2009: 89-94 - 2008
- [c3]Seunghwan Hyun, Sehwan Lee, Sungyong Ahn, Kern Koh:
Improving the Demand Paging Performance with NAND-type Flash Memory. ICCSA Workshops 2008: 157-163 - [c2]Seunghwan Hyun, Sehwan Lee, Sungyong Ahn, Hyokyung Bahn, Kern Koh:
Vector Read: Exploiting the Read Performance of Hybrid NAND Flash. RTCSA 2008: 177-184 - 2007
- [c1]Seunghwan Hyun, Sungyong Ahn, Sehwan Lee, Hyokyung Bahn, Kern Koh:
Memory-Efficient Compressed Filesystem Architecture for NAND Flash-Based Embedded Systems. ICCSA (1) 2007: 252-264
Coauthor Index
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