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ORCIDKatarína Jelemenská
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2020 – today
- 2020
[j3]Michal Skuta, Dominik Macko
, Katarína Jelemenská:
Automation of Dynamic Power Management in FPGA-Based Energy-Constrained Systems. IEEE Access 8: 165894-165903 (2020)
2010 – 2019
- 2018
- [j2]Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation. Integr. 63: 101-114 (2018) - 2017
- [j1]Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Verification of Power-Management Specification at Early Stages of Power-Constrained Systems Design. J. Circuits Syst. Comput. 26(8): 1740002:1-1740002:23 (2017) - [c10]Miroslav Siro, Dominik Macko, Katarína Jelemenská:
PMS2UPF: An automated transition from ESL to RTL power-intent specification. DDECS 2017: 140-144 - 2016
- [c9]Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Early-stage verification of power-management specification in low-power systems design. DDECS 2016: 157-162 - 2015
- [c8]Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Power-Management Specification in SystemC. DDECS 2015: 259-262 - [c7]Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Power-management high-level synthesis. VLSI-SoC 2015: 63-68 - 2014
- [c6]Dominik Macko, Katarína Jelemenská:
Self-managing power management unit. DDECS 2014: 159-162 - [c5]Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Power-efficient power-management logic. PATMOS 2014: 1-7 - 2013
- [c4]Katarína Jelemenská, Martin Hyben, Tomás Janciga, Martin Kardos, Lubomír Maron, Zsolt Süll:
Extensible framework for graphical representation of HDL models and Simulation Results. AFRICON 2013: 1-5 - [c3]Dominik Macko, Katarína Jelemenská:
Managing digital-system power at the system level. AFRICON 2013: 1-5 - 2012
- [c2]Dominik Macko, Katarína Jelemenská:
VHDLVisualizer: HDL model visualization with simulation-based verification. DDECS 2012: 199-200 - 2011
- [c1]Dominik Macko, Katarína Jelemenská:
VHDL structural model visualization. EUROCON 2011: 1-4
Coauthor Index
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