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2020 – today
- 2023
[j3]Kwang-Hoon Lee
, Jung-Hun Park, Yongjae Lee, Yeonggeun Song, Seungha Roh, Minkyo Shim, Yoonho Song, Woosong Jung, Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong:
A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4003-4007 (2023)- [c2]Woosong Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong:
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces. CICC 2023: 1-2 - 2022
- [j2]Yeonggeun Song, Han-Gon Ko, Changhyun Kim, Deog-Kyoon Jeong:
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 759-763 (2022) - [c1]Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong:
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC 2022: 249-252
2010 – 2019
- 2019
- [j1]Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong:
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1932-1936 (2019)
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