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2020 – today
- 2024
[j35]Kirti Gupta
, Bijaya Ketan Panigrahi, Anupam Joshi, Kolin Paul:
Demonstration of denial of charging attack on electric vehicle charging infrastructure and its consequences. Int. J. Crit. Infrastructure Prot. 46: 100693 (2024)- [c98]Nikki Tiwari, Kolin Paul, Shrawan Kumar Raut, Animesh Ray, Surabhi Vyas, Naveet Wig:
MMTS: Multi-Modal Time Series Based Decision Support System for Ventilator Associated Pneumonia. IJCNN 2024: 1-8 - [c97]Vijay Kumar, Goldy, Kolin Paul, Mahesh Chowdhary:
Long Short Term Memory (LSTM)-based Cuffless Continuous Blood Pressure Monitoring. VLSID 2024: 330-335 - [c96]Avishek Choudhury, Brototi Mondal, Kolin Paul, Biplab K. Sikdar:
LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore. VLSID 2024: 690-695 - [i5]Vijay Kumar, Kolin Paul:
Medical Image Data Provenance for Medical Cyber-Physical System. CoRR abs/2403.15522 (2024) - 2023
- [j34]Vijay Kumar, Kolin Paul:
Device Fingerprinting for Cyber-Physical Systems: A Survey. ACM Comput. Surv. 55(14s): 302:1-302:41 (2023) - [j33]Vijay Kumar, Kolin Paul:
Fundus Imaging-Based Healthcare: Present and Future. ACM Trans. Comput. Heal. 4(3): 16:1-16:34 (2023) - [j32]Vijay Kumar, Het Patel, Kolin Paul, Shorya Azad:
Deep Learning-assisted Retinopathy of Prematurity (ROP) Screening. ACM Trans. Comput. Heal. 4(3): 18:1-18:32 (2023) - [j31]Avishek Choudhury, Brototi Mondal, Kolin Paul, Biplab K. Sikdar:
Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor. Microprocess. Microsystems 101: 104864 (2023) - [j30]Astha Chawla, Prakhar Agrawal, Bijaya Ketan Panigrahi, Kolin Paul:
Deep-learning-based data-manipulation attack resilient supervisory backup protection of transmission lines. Neural Comput. Appl. 35(7): 4835-4854 (2023) - [c95]Vijay Kumar, Vatsal Agrawal, Shorya Azad, Kolin Paul:
Deep Learning Assisted Plus Disease Screening of Retinal Image of Infants. HEALTHINF 2023: 538-545 - [c94]Suyash Saxena, Varun Singh Negi, Kolin Paul:
Compression of Large LSTM Networks for Inference on Space Constraint Systems. PReMI 2023: 137-146 - 2022
- [j29]Saurabh Tewari, Anshul Kumar, Kolin Paul:
Minimizing Off-Chip Memory Access for CNN Accelerators. IEEE Consumer Electron. Mag. 11(3): 95-104 (2022) - [j28]Geeta Yadav, Praveen Gauravaram, Arun Kumar Jindal, Kolin Paul:
SmartPatch: A patch prioritization framework. Comput. Ind. 137: 103595 (2022) - [j27]Astha Chawla, Animesh Singh, Prakhar Agrawal, Bijaya Ketan Panigrahi, Bhavesh R. Bhalja, Kolin Paul:
Denial-of-Service Attacks Pre-Emptive and Detection Framework for Synchrophasor Based Wide Area Protection Applications. IEEE Syst. J. 16(1): 1570-1581 (2022) - [c93]Vijay Kumar, Het Patel, Kolin Paul, Abhidnya Surve, Shorya Azad, Rohan Chawla:
Improved Blood Vessels Segmentation of Retinal Image of Infants. HEALTHINF 2022: 142-153 - [c92]Vijay Kumar, Het Patel, Shorya Azad, Kolin Paul:
Improved Blood Vessels Segmentation of Infant Retinal Image. BIOSTEC (Selected Papers) 2022: 288-314 - [c91]Saurabh Tewari, Anshul Kumar, Kolin Paul:
SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators. DATE 2022: 580-583 - 2021
- [j26]Rajesh Kedia, Shikha Goel, M. Balakrishnan, Kolin Paul, Rijurekha Sen:
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators. IEEE Embed. Syst. Lett. 13(3): 114-117 (2021) - [j25]Geeta Yadav, Kolin Paul:
Architecture and security of SCADA systems: A review. Int. J. Crit. Infrastructure Prot. 34: 100433 (2021) - [c90]Vijay Kumar, Het Patel, Kolin Paul, Abhidnya Surve, Shorya Azad, Rohan Chawla:
Deep Learning Assisted Retinopathy of Prematurity Screening Technique. HEALTHINF 2021: 234-243 - [c89]Vijay Kumar, Het Patel, Shorya Azad, Kolin Paul, Abhidnya Surve, Rohan Chawla:
DL-Assisted ROP Screening Technique. BIOSTEC (Selected Papers) 2021: 236-258 - [c88]Yu Yang, Ahmed Hemani, Kolin Paul:
Scheduling Persistent and Fully Cooperative Instructions. DSD 2021: 229-237 - [c87]Yu Yang, Ahmed Hemani, Kolin Paul:
Scheduling Persistent and Fully Cooperative Instructions. FCCM 2021: 274 - [c86]Vijay Kumar, Kolin Paul:
DevFing: Robust LCR Based Device Fingerprinting. MECO 2021: 1-6 - [c85]Geeta Yadav, Kolin Paul:
Global Monitor using SpatioTemporally Correlated Local Monitors. NCA 2021: 1-10 - 2020
- [j24]Astha Chawla, Prakhar Agrawal, Animesh Singh, Bijaya Ketan Panigrahi, Kolin Paul, Bhavesh R. Bhalja:
Denial-of-Service Resilient Frameworks for Synchrophasor-Based Wide Area Monitoring Systems. Computer 53(5): 14-24 (2020) - [j23]Geeta Yadav, Kolin Paul, Alaa M. Allakany, Koji Okamura:
IoT-PEN: An E2E Penetration Testing Framework for IoT. J. Inf. Process. 28: 633-642 (2020) - [j22]Ahmed Hemani, Muhammad Shafique, Kolin Paul:
Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks. J. Signal Process. Syst. 92(11): 1215-1217 (2020) - [c84]Alaa M. Allakany, Geeta Yadav, Kolin Paul, Koji Okamura:
Detection and Mitigation of LFA Attack in SDN-IoT Network. AINA Workshops 2020: 1087-1096 - [c83]Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil:
A Security Verification Template to Assess Cache Architecture Vulnerabilities. DDECS 2020: 1-6 - [c82]Geeta Yadav, Kolin Paul, Alaa M. Allakany, Koji Okamura:
IoT-PEN: A Penetration Testing Framework for IoT. ICOIN 2020: 196-201 - [c81]B. Shanker Jaiswal, B. Chandra, Kolin Paul:
Geodetic Distance and Dynamic Outlier Exclusion in EM Optimization of Self Exciting Point Process for Homicide Prediction in Chicago. IIAI-AAI 2020: 534-541 - [c80]Ameer Shalabi, Kolin Paul, Tara Ghasempouri, Jaan Raik:
NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad. ISVLSI 2020: 54-59 - [c79]Saurabh Tewari, Anshul Kumar, Kolin Paul:
Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators. ISVLSI 2020: 240-245 - [c78]Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul:
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. VLSI-SOC 2020: 16-21 - [i4]Geeta Yadav, Kolin Paul:
Architecture and Security of SCADA Systems: A Review. CoRR abs/2001.02925 (2020) - [i3]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. CoRR abs/2002.11108 (2020) - [i2]Sourav Das, Samuel Wedaj, Kolin Paul, Umesh Bellur, Vinay Joseph Ribeiro:
Airmed: Efficient Self-Healing Network of Low-End Devices. CoRR abs/2004.12442 (2020) - [i1]Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul:
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. CoRR abs/2008.08409 (2020)
2010 – 2019
- 2019
- [j21]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority. J. Electron. Test. 35(5): 679-694 (2019) - [j20]Samuel Wedaj, Kolin Paul, Vinay J. Ribeiro:
DADS: Decentralized Attestation for Device Swarms. ACM Trans. Priv. Secur. 22(3): 19:1-19:29 (2019) - [c77]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress. CODES+ISSS 2019: 12:1-12:2 - [c76]Rajesh Kedia, M. Balakrishnan, Kolin Paul:
GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems. DSD 2019: 4-12 - [c75]Geeta Yadav, Kolin Paul:
PatchRank: Ordering updates for SCADA systems. ETFA 2019: 110-117 - [c74]Geeta Yadav, Kolin Paul:
Assessment of SCADA System Vulnerabilities. ETFA 2019: 1737-1744 - [c73]Geeta Yadav, Alaa M. Allakany, Vijay Kumar, Kolin Paul, Koji Okamura:
Penetration Testing Framework for IoT. IIAI-AAI 2019: 477-482 - [c72]Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul:
PASCAL: Timing SCA Resistant Design and Verification Flow. IOLTS 2019: 239-242 - [c71]Dimitrios Stathis, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred G. Grabherr, Rafi Ahmad:
Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. ISVLSI 2019: 560-567 - [c70]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. VLSID 2019: 464-469 - 2018
- [j19]Niladri Sekhar Tripathy, Indra Narayan Kar, Kolin Paul:
Suboptimal robust stabilization of discrete-time mismatched nonlinear system. IEEE CAA J. Autom. Sinica 5(1): 352-359 (2018) - [c69]Sapna Sapna, N. S. Sreenivasalu, Kolin Paul:
DAPP: Accelerating Training of DNN. HPCC/SmartCity/DSS 2018: 867-872 - [c68]Yu Yang, Dimitrios Stathis, Prashant Sharma, Kolin Paul, Ahmed Hemani, Manfred G. Grabherr, Rafi Ahmad:
RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. SAMOS 2018: 105-114 - 2017
- [j18]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
Hardware acceleration of de novo genome assembly. Int. J. Embed. Syst. 9(1): 74-89 (2017) - [j17]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. Int. J. Parallel Program. 45(6): 1420-1460 (2017) - [j16]Niladri Sekhar Tripathy, I. N. Kar, Kolin Paul:
Stabilization of Uncertain Discrete-Time Linear System With Limited Communication. IEEE Trans. Autom. Control. 62(9): 4727-4733 (2017) - [j15]Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn:
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. J. Signal Process. Syst. 87(3): 327-341 (2017) - [c67]Varan Gupta, Rohit Patel, Gaurav Sardal, Jyotirmoy Ray, Subir Kumar Saha, Kolin Paul:
Design and Development of Robots for ABU Robocon 2016. AIR 2017: 13:1-13:6 - [c66]Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Kolin Paul, Naeem Abbas:
MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks. IPDPS 2017: 276-286 - 2016
- [j14]Rajesh Kumar Pal, Ierum Shanaya, Kolin Paul, Sanjiva Prasad:
Dynamic core allocation for energy efficient video decoding in homogeneous and heterogeneous multicore architectures. Future Gener. Comput. Syst. 56: 247-261 (2016) - [j13]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen:
Polymorphic Configuration Architecture for CGRAs. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 403-407 (2016) - [c65]Vijay Kumar, Kolin Paul:
mNetra: A Fundoscopy based Optometer. HEALTHINF 2016: 83-92 - [c64]Shalini Singh, Kolin Paul, Geeta Yadav, Sanjiva Prasad:
prasavGraph: Android based Labour Monitoring. HEALTHINF 2016: 458-466 - [c63]Gaurav Jain, Lalchand Rathore, Kolin Paul:
GAMS: Genome Assembly on Multi-GPU Using String Graph. HPCC/SmartCity/DSS 2016: 348-355 - 2015
- [j12]Arun Parakh, M. Balakrishnan, Kolin Paul:
Improving Map-Reduce for GPUs with cache. Int. J. High Perform. Syst. Archit. 5(3): 166-177 (2015) - [j11]Syed M. A. H. Jafri, Ozan Ozbag, Nasim Farahini, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs. ACM J. Emerg. Technol. Comput. Syst. 11(4): 40:1-40:29 (2015) - [j10]Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung:
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2079-2090 (2015) - [c62]Niladri Sekhar Tripathy, Indra Narayan Kar, Kolin Paul:
Finite-time robust control of robot manipulator: a SDDRE based approach. AIR 2015: 56:1-56:6 - [c61]Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul:
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. ARC 2015: 373-382 - [c60]Kolin Paul, Vijay Kumar:
Fundus Imaging Based Affordable Eye Care. HEALTHINF 2015: 634-641 - [c59]Pei Liu, Ahmed Hemani, Kolin Paul:
3D-stacked many-core architecture for biological sequence analysis problems. SAMOS 2015: 211-220 - 2014
- [j9]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33(11): 3499-3526 (2014) - [j8]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18(3-4): 295-327 (2014) - [j7]Rajesh Kumar Pal, Kolin Paul, Sanjiva Prasad:
ReKonf: Dynamically reconfigurable multiCore architecture. J. Parallel Distributed Comput. 74(11): 3071-3086 (2014) - [j6]Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul:
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. Microprocess. Microsystems 38(8): 788-802 (2014) - [j5]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 521-525 (2014) - [c58]Anju Kansal, Avval Gupta, Kolin Paul, Sanjiva Prasad:
mDROID - An Affordable Android based mHealth System. HEALTHINF 2014: 109-116 - [c57]Avval Gupta, Anju Kansal, Kolin Paul, Sanjiva Prasad:
A Modular Android-Based Multi-sensor mHealth System. BIOSTEC (Selected Papers) 2014: 360-377 - [c56]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Morphable Compression Architecture for Efficient Configuration in CGRAs. DSD 2014: 42-49 - [c55]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. DSD 2014: 66-73 - [c54]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Customizable Compression Architecture for Efficient Configuration in CGRAs. FCCM 2014: 31 - [c53]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array. FCCM 2014: 33 - [c52]Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
TransPar: Transformation based dynamic Parallelism for low power CGRAs. FPL 2014: 1-8 - [c51]Rajesh Kumar Pal, Kolin Paul, Sanjiva Prasad:
Energy Efficient Dynamic Core Allocation for Video Decoding in Embedded Multicore Architectures. HPCC/CSS/ICESS 2014: 653-660 - [c50]Niladri Sekhar Tripathy, I. N. Kar, Kolin Paul:
An event-triggered based robust control of robot manipulator. ICARCV 2014: 425-430 - [c49]Pei Liu, Ahmed Hemani, Kolin Paul:
A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture. ISSoC 2014: 1-8 - [c48]Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul:
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI 2014: 332-337 - [c47]Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. ICSAMOS 2014: 233-241 - [c46]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. VLSID 2014: 306-311 - 2013
- [j4]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. Microprocess. Microsystems 37(8-A): 811-822 (2013) - [c45]Aarathi Prasad, Ronald A. Peterson, Shrirang Mare, Jacob Sorber, Kolin Paul, David Kotz:
Provenance framework for mHealth. COMSNETS 2013: 1-6 - [c44]Nasim Farahini, Ahmed Hemani, Kolin Paul:
Distributed Runtime Computation of Constraints for Multiple Inner Loops. DSD 2013: 389-395 - [c43]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD 2013: 525-534 - [c42]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
FAssem: FPGA Based Acceleration of De Novo Genome Assembly. FCCM 2013: 173-176 - [c41]Ashutosh Jain, Anshuj Garg, Kolin Paul:
GAGM: Genome assembly on GPU using mate pairs. HiPC 2013: 176-185 - [c40]Anshuj Garg, Ashutosh Jain, Kolin Paul:
GGAKE: GPU Based Genome Assembly Using K-Mer Extension. HPCC/EUC 2013: 1105-1112 - [c39]Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs. IPDPS Workshops 2013: 202-211 - [c38]U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar:
High performance 3D-FFT implementation. ISCAS 2013: 2227-2230 - [c37]Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. ISQED 2013: 104-111 - [c36]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC 2013: 1-8 - [c35]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs. ICSAMOS 2013: 104-112 - [c34]B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan:
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design 2013: 92-97 - 2012
- [c33]Kolin Paul, Chinmaya Dash, Mansureh Shahraki Moghaddam:
reMORPH: A Runtime Reconfigurable Architecture. DSD 2012: 26-33 - [c32]Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. DSD 2012: 242-249 - [c31]Pei Liu, Ahmed Hemani, Kolin Paul:
Improved Bioinformatics Processing Unit for Multiple Applications. IPDPS Workshops 2012: 390-396 - [c30]Arun Parakh, M. Balakrishnan, Kolin Paul:
Performance Estimation of GPUs with Cache. IPDPS Workshops 2012: 2384-2393 - [c29]Rajesh Kumar Pal, Kolin Paul, Sanjiva Prasad:
ReKonf: A Reconfigurable Adaptive ManyCore Architecture. ISPA 2012: 182-191 - [c28]Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen:
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS 2012: 450-458 - 2011
- [j3]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. 7(3): 13:1-13:20 (2011) - [j2]Tapas Kumar Kundu, Kolin Paul:
Analyzing and Improving Performance and Energy Efficiency of Android. J. Low Power Electron. 7(4): 516-528 (2011) - [c27]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Architecture and tools for programmable QCA. FPT 2011: 1-4 - [c26]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. FPT 2011: 1-6 - [c25]Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures. IPDPS Workshops 2011: 290-293 - [c24]Pei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul:
A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics. ReConFig 2011: 190-197 - [c23]Pei Liu, Ahmed Hemani, Kolin Paul:
A Reconfigurable Processor for Phylogenetic Inference. VLSI Design 2011: 226-231 - [c22]Tapas Kumar Kundu, Kolin Paul:
Improving Android Performance and Energy Efficiency. VLSI Design 2011: 256-261 - 2010
- [c21]Kolin Paul, Tapas Kumar Kundu:
Android on Mobile Devices: An Energy Perspective. CIT 2010: 2421-2426 - [c20]Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712 - [c19]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
A tiled programmable fabric using QCA. FPT 2010: 9-16 - [c18]Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Clocking-Based Coplanar Wire Crossing Scheme for QCA. VLSI Design 2010: 339-344
2000 – 2009
- 2008
- [c17]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. VLSI Design 2008: 261-266 - [c16]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. VLSI Design 2008: 348-353 - 2007
- [c15]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Recurring Pattern Identification and its Application to Instruction Set Extension. CDES 2007: 67-73 - [c14]Kolin Paul, Joël Porquet, Josep Llosa:
Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. DSD 2007: 317-324 - [c13]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Application Specific Datapath Extension with Distributed I/O Functional Units. VLSI Design 2007: 551-558 - 2006
- [c12]Nilesh Padhariya, Kolin Paul, Dheeraj Bhardwaj:
A FLOPs Based Model for Performance Analysis and Scheduling of Applications for Single and Multiple CPUs. ICPP Workshops 2006: 455-464 - [c11]Rahul Jain, Anindita Mukherjee, Kolin Paul:
Defect-Aware Design Paradigm for Reconfigurable Architectures. ISVLSI 2006: 91-96 - 2005
- [c10]Sanjay V. Rajopadhye, Kolin Paul:
A 1.5-D Architecture for Back-Propagation Training. ERSA 2005: 112-118 - [c9]Kolin Paul:
An FPGA Based Test Bed for Bio Inspired Computation. IPDPS 2005 - 2002
- [j1]Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri:
Theory of Extended Linear Machines. IEEE Trans. Computers 51(9): 1106-1110 (2002) - 2000
- [c8]Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar:
Theory and Applications of Cellular Automata for VLSI Design and Testing. VLSI Design 2000: 4 - [c7]Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury:
GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. VLSI Design 2000: 140-143 - [c6]Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury:
Scalable Pipelined Micro-Architecture for Wavelet Transform. VLSI Design 2000: 144- - [c5]Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee:
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. VLSI Design 2000: 556-561 - [c4]Kolin Paul, Dipanwita Roy Chowdhury:
Application of GF(2p) CA in Burst Error Correcting Codes. VLSI Design 2000: 562-567
1990 – 1999
- 1999
- [c3]Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri:
Cellular Automata Based Transform Coding for Image Compression. HiPC 1999: 269-273 - [c2]Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri:
A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. VLSI Design 1999: 532-537 - 1998
- [c1]Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri:
Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. Asian Test Symposium 1998: 388-
Coauthor Index
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