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Daniel Chillet
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2020 – today
- 2024
- [c51]Léo Pradels, Silviu-Ioan Filip, Olivier Sentieys, Daniel Chillet, Thibaut Le Calloch:
FPGA-based CNN Acceleration using Pattern-Aware Pruning. AICAS 2024: 228-232 - [c50]Wilfread Guillemé, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet:
HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks. DAC 2024: 270:1-270:6 - [c49]Wilfread Guillemé, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet:
VANDOR: Mitigating SEUs into Quantized Neural Networks. IOLTS 2024: 1-6 - [c48]Hamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau:
Mitigation of Hardware Trojan in NoC using Delta-Based Compression. SOCC 2024: 1-6 - [e7]Lilia Zaourar, Daniel Chillet, Daniel Gracia Pérez, Morteza Biglari-Abhari, Réda Nouacer, Matthias Jung, Gianluca Palermo:
Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, RAPIDO 2024, Munich, Germany, 18 January 2024. ACM 2024 [contents] - 2023
- [j19]Ibrahim Krayem, Joel Ortiz Sosa, Cédric Killian, Daniel Chillet:
Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs. IEEE Des. Test 40(6): 136-148 (2023) - 2022
- [j18]Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet:
BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2276-2289 (2022) - [j17]Jaechul Lee, Cédric Killian, Sébastien Le Beux, Daniel Chillet:
Distance-aware Approximate Nanophotonic Interconnect. ACM Trans. Design Autom. Electr. Syst. 27(2): 17:1-17:30 (2022) - [c47]Ibrahim Krayem, Romain Mercier, Cédric Killian, Angeliki Kritikakou, Daniel Chillet:
Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing. NANOARCH 2022: 17:1-17:6 - 2021
- [c46]Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet:
A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency. DFT 2021: 1-4 - [e6]Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings. Lecture Notes in Computer Science 12700, Springer 2021, ISBN 978-3-030-79024-0 [contents] - 2020
- [j16]Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet:
Energy-Efficient Scheduling of Real-Time Tasks in Reconfigurable Homogeneous Multicore Platforms. IEEE Trans. Syst. Man Cybern. Syst. 50(12): 5092-5105 (2020) - [c45]Romain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet:
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture. ICCD 2020: 205-212
2010 – 2019
- 2019
- [c44]Jaechul Lee, Cédric Killian, Sébastien Le Beux, Daniel Chillet:
Approximate nanophotonic interconnects. NOCS 2019: 9:1-9:7 - [e5]Daniel Chillet:
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO 2019, Valencia, Spain, January 21-23, 2019. ACM 2019, ISBN 978-1-4503-6260-3 [contents] - 2018
- [j15]Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Olivier Sentieys, Ian O'Connor:
Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects. ACM J. Emerg. Technol. Comput. Syst. 14(2): 24:1-24:19 (2018) - [c43]Jiating Luo, Van-Dung Pham, Cédric Killian, Daniel Chillet, Ian O'Connor, Olivier Sentieys, Sébastien Le Beux:
Run-Time management of energy-performance trade-off in Optical Network-on-Chip. DCIS 2018: 1-6 - [c42]Aymen Gammoudi, Daniel Chillet, Mohamed Khalgui, Adel Benzina:
Mapping of Periodic Tasks in Reconfigurable Heterogeneous Multi-core Platforms. ENASE 2018: 99-110 - [e4]Daniel Chillet:
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Manchester, UK, January 22-24, 2018. ACM 2018, ISBN 978-1-4503-6417-1 [contents] - 2017
- [c41]Cédric Killian, Daniel Chillet, Sébastien Le Beux, Van-Dung Pham, Olivier Sentieys, Ian O'Connor:
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. DAC 2017: 85:1-85:6 - [c40]Jiating Luo, A. Elantably, Van-Dung Pham, Cédric Killian, Daniel Chillet, Sébastien Le Beux, Olivier Sentieys, Ian O'Connor:
Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC. DATE 2017: 1372-1377 - 2016
- [j14]Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys:
Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems. J. Low Power Electron. 12(3): 172-185 (2016) - [c39]Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet:
Real-Time Scheduling of Reconfigurable Battery-Powered Multi-Core Platforms. ICTAI 2016: 121-129 - 2015
- [c38]Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys:
Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip. SiPhotonics@HiPEAC 2015: 33-39 - [c37]Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cédric Killian, Daniel Chillet, Hui Li, Ian O'Connor, Olivier Sentieys:
Communication Aware Design Method for Optical Network-on-Chip. MCSoC 2015: 243-250 - [c36]Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet:
New Pack Oriented Solutions for Energy-Aware Feasible Adaptive Real-Time Systems. SoMeT 2015: 73-86 - [e3]Gianluca Palermo, Daniel Gracia Pérez, Morteza Biglari-Abhari, Daniel Chillet, Smaïl Niar, Adam Morawiec:
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015, Amsterdam, The Netherlands. ACM 2015, ISBN 978-1-60558-699-1 [contents] - 2014
- [j13]Daniel Chillet, Michael Hübner:
Special issue on design and architectures of real-time image processing in embedded systems. J. Real Time Image Process. 9(1): 1-3 (2014) - [j12]Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys:
Power consumption models for the use of dynamic and partial reconfiguration. Microprocess. Microsystems 38(8): 860-872 (2014) - [c35]Quang-Hai Khuat, Daniel Chillet, Michael Hübner:
Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA. AHS 2014: 1-8 - [c34]Rajhans Singh, Daniel Chillet:
Intrinsic Fault Tolerance of Hopfield Artificial Neural Network Model for Task Scheduling Technique in SoC. IJCCI (NCTA) 2014: 288-293 - [c33]Quang-Hai Khuat, Daniel Chillet, Michael Hübner:
Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC. ReConFig 2014: 1-4 - [e2]Daniel Gracia Pérez, Morteza Biglari-Abhari, Daniel Chillet, Gianluca Palermo:
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '14, 22 January, 2014, Vienna, Austria. ACM 2014, ISBN 978-1-4503-2471-7 [contents] - 2013
- [j11]Rabie Ben Atitallah, Eric Senn, Daniel Chillet, Mickael Lanoe, Dominique Blouin:
An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC. IEEE Trans. Ind. Informatics 9(1): 487-501 (2013) - [c32]Quang-Hai Khuat, Daniel Chillet:
Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource. DASIP 2013: 265-270 - [c31]Quang-Hai Khuat, Quang-Hoa Le, Daniel Chillet, Sébastien Pillement:
Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture. IDT 2013: 1-6 - 2012
- [c30]Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Rabie Ben Atitallah, A. Fritsch, Christian Samoyeau:
Open-people: An open platform for estimation and optimizations of energy consumption. DASIP 2012: 1-2 - [c29]Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet:
UPaRC - Ultra-fast power-aware reconfiguration controller. DATE 2012: 1373-1378 - [c28]Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Sébastien Bilavarn, Rabie Ben Atitallah, Christian Samoyeau, A. Fritsch:
Open-People: Open Power and Energy Optimization PLatform and Estimator. DSD 2012: 668-675 - [c27]Robin Bonamy, Daniel Chillet, Sébastien Bilavarn, Olivier Sentieys:
Power consumption model for partial and dynamic reconfiguration. ReConFig 2012: 1-8 - [e1]Daniel Gracia Pérez, Morteza Biglari-Abhari, Daniel Chillet, Gianluca Palermo:
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO '13, 21 January, 2013, Berlin, Germany. ACM 2012, ISBN 978-1-4503-1539-5 [contents] - 2011
- [j10]Dominique Blouin, Daniel Chillet, Eric Senn, Sébastien Bilavarn, Robin Bonamy, Christian Samoyeau:
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. Int. J. Reconfigurable Comput. 2011: 425401:1-425401:15 (2011) - [j9]Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys:
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. J. Syst. Archit. 57(4): 340-353 (2011) - [j8]Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sébastien Bilavarn:
Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. SIGARCH Comput. Archit. News 39(4): 104-105 (2011) - [c26]Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Parallel Evaluation of Hopfield Neural Networks. IJCCI (NCTA) 2011: 248-253 - [c25]Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Hardware OS Communication Service and Dynamic Memory Management for RSoCs. ReConFig 2011: 117-122 - [c24]Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sébastien Bilavarn:
Towards a power and energy efficient use of partial dynamic reconfiguration. ReCoSoC 2011: 1-4 - [c23]Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. VLSI-SoC 2011: 196-199 - 2010
- [j7]Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2010: 390545:1-390545:15 (2010) - [c22]Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Task placement for dynamic and partial reconfigurable architecture. DASIP 2010: 228-234 - [c21]Daniel Chillet:
Open-People: Open Power and Energy Optimization PLatform and Estimator. PATMOS 2010: 251 - [c20]Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. ReConFig 2010: 376-381 - [c19]Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Mesh and Fat-Tree comparison for dynamically reconfigurable applications. ReCoSoC 2010: 157-160
2000 – 2009
- 2009
- [j6]Benoît Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, Thomas LeFebvre, Mehdi Aïchouch, Jean-Christophe Prévotet, Yaset Oliva, Daniel Chillet, Sébastien Pillement:
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. Int. J. Reconfigurable Comput. 2009: 450607:1-450607:22 (2009) - [c18]Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet:
High-Level Exploration for Dynamic Reconfiguration Management. ERSA 2009: 301-302 - 2008
- [j5]Daniel Chillet, Raphaël David, Erwan Grâce, Olivier Sentieys:
Structure mémoire reconfigurable. Vers une structure de stockage faible consommation. Tech. Sci. Informatiques 27(1-2): 181-202 (2008) - [c17]Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement:
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig 2008: 61-66 - 2007
- [c16]Imene Benkermi, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Hardware task scheduling for heterogeneous soc architectures. EUSIPCO 2007: 1653-1657 - [c15]Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN 2007: 102-107 - 2006
- [j4]Daniel Ménard, Daniel Chillet, Olivier Sentieys:
Floating-to-Fixed-Point Conversion for Digital Signal Processors. EURASIP J. Adv. Signal Process. 2006 (2006) - 2005
- [c14]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34 - [c13]François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement:
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC 2005: 71-78 - 2003
- [j3]Daniel Ménard, Taofik Saïdi, Daniel Chillet, Olivier Sentieys:
Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. Tech. Sci. Informatiques 22(6): 783-803 (2003) - 2002
- [c12]Daniel Ménard, Daniel Chillet, François Charot, Olivier Sentieys:
Automatic floating-point to fixed-point conversion for DSP code generation. CASES 2002: 270-276 - [c11]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL 2002: 1058-1067 - [c10]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture. ICASSP 2002: 4194 - [c9]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS 2002 - [c8]Sébastien Pillement, Daniel Chillet, Olivier Sentieys:
Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED 2002: 388-393 - 2001
- [c7]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC 2001: 51-62 - 2000
- [j2]Hélène Dubois, Olivier Sentieys, Daniel Chillet, Jean Luc Philippe:
Teaching hardware/software system codesign using CAD tools: a case study in image synthesis. IEEE Trans. Educ. 43(3): 277-283 (2000) - [j1]Jean-Philippe Diguet, Daniel Chillet, Olivier Sentieys:
A Framework for High Level Estimations of Signal Processing VLSI Implementations. J. VLSI Signal Process. 25(3): 261-284 (2000) - [c6]Jean-Gabriel Cousin, Olivier Sentieys, Daniel Chillet:
Multi-algorithm ASIP synthesis and power estimation for DSP applications. ISCAS 2000: 621-624
1990 – 1999
- 1999
- [c5]Daniel Chillet, Olivier Sentieys, Michel Corazza:
Memory Unit Design for Real Time DSP Applications. Great Lakes Symposium on VLSI 1999: 260- - [c4]J. O. Dedou, Daniel Chillet, Olivier Sentieys:
Behavioral synthesis of asynchronous systems: a methodology. ISCAS (6) 1999: 370-373 - 1998
- [c3]J. Okito Dedou, Daniel Chillet, Olivier Sentieys:
Asynchronous timing model for high-level synthesis of DSP applications. EUSIPCO 1998: 1-4 - 1997
- [c2]Jean-Philippe Diguet, Olivier Sentieys, Daniel Chillet, Jean Luc Philippe:
VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters. ICASSP 1997: 671-674 - 1996
- [c1]Jean Luc Philippe, Daniel Chillet, Olivier Sentieys, Jean-Philippe Diguet:
Memory aspects in signal processing and HLS tool: Some results. EUSIPCO 1996: 1-4
Coauthor Index
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last updated on 2024-12-02 22:33 CET by the dblp team
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