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2010 – 2019
- 2018
[j3]Shady O. Agwa
, Eslam Yahya, Yehea Ismail:
A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1909-1918 (2018)- 2017
- [c18]Shady O. Agwa, Eslam Yahya, Yehea Ismail:
Power efficient AES core for IoT constrained devices implemented in 130nm CMOS. ISCAS 2017: 1-4 - [c17]Nada El-meligy, Moustafa Amin, Eslam Yahya, Yehea Ismail:
130nm Low power asynchronous AES core. ISCAS 2017: 1-4 - 2016
- [j2]Shady O. Agwa, Eslam Yahya, Yehea Ismail:
ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing. IEEE Trans. Circuits Syst. II Express Briefs 63-II(11): 1069-1073 (2016) - [c16]Eslam Amr, Marina Maher, Amir Rashad, Mohamed Raafat, Yosif Diaa, Eslam Yahya, Yehea Ismail:
Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology. ICM 2016: 325-328 - [c15]Tarek Ramadan, Eslam Yahya, Mohamed Dessouky, Yehea Ismail:
Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis. ISCAS 2016: 1930-1933 - 2015
- [j1]Karim Ali, Eslam Yahya, Alaa B. El-Rouby, Yehea I. Ismail:
Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays. Microelectron. J. 46(12): 1291-1303 (2015) - [c14]Kareem Ali, Eslam Yahya, Alaa B. El-Rouby, Yehea Ismail:
Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays. ICEAC 2015: 1-4 - [c13]Tarek Ramadan, Eslam Yahya, Mohamed Dessouky, Yehea I. Ismail:
Coupling capacitance extraction in through-silicon via (TSV) arrays. ICECS 2015: 470-473 - [c12]Eslam Yahya, Hatem Zakaria, Yehea Ismail:
Deadlock detection in conditional asynchronous circuits under mismatched branch selection. ICECS 2015: 596-600 - 2013
- [c11]Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin:
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC 2013: 67-74 - [c10]Shady O. Agwa, Eslam Yahya, Yehea I. Ismail:
Variability mitigation using correction function technique. ICECS 2013: 293-296 - 2010
- [c9]Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet:
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. PATMOS 2010: 137-149 - [c8]Oussama Elissati, Sébastien Rieubon, Eslam Yahya, Laurent Fesquet:
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. VLSI-SoC (Selected Papers) 2010: 22-42 - [c7]Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet:
A high-speed high-resolution low-phase noise oscillator using self-timed rings. VLSI-SoC 2010: 173-178
2000 – 2009
- 2009
- [c6]Eslam Yahya, Oussama Elissati, Hatem Zakaria, Laurent Fesquet, Marc Renaudin:
Programmable/Stoppable Oscillator Based on Self-Timed Rings. ASYNC 2009: 3-12 - [c5]Eslam Yahya, Laurent Fesquet:
Asynchronous design: A promising paradigm for electronic circuits and systems. ICECS 2009: 339-342 - 2008
- [c4]Eslam Yahya, Marc Renaudin:
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. ICECS 2008: 1285-1289 - 2007
- [c3]Eslam Yahya, Marc Renaudin:
Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. ICECS 2007: 1288-1291 - 2006
- [c2]Eslam Yahya, Marc Renaudin:
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS 2006: 583-592 - 2003
- [c1]François Charot, Eslam Yahya, Charles Wagner:
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. FPL 2003: 282-291
Coauthor Index
aka: Yehea Ismail
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