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2020 – today
- 2022
[c8]Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto:
28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. VLSI-DAT 2022: 1-4
2010 – 2019
- 2017
- [c7]Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura:
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA 2017: 290 - 2016
- [j6]Hiroki Nakahara
, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura:
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 73-86 (2016) - [j5]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto:
An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k). J. Multiple Valued Log. Soft Comput. 26(1-2): 109-123 (2016) - [c6]Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. CCNC 2016: 309-314 - [c5]Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura:
A memory-based realization of a binarized deep convolutional neural network. FPT 2016: 277-280 - 2015
- [j4]Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto, Yasuhiro Terao:
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. IEICE Trans. Inf. Syst. 98-D(2): 262-271 (2015) - 2013
- [j3]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. IEICE Trans. Commun. 96-B(7): 1819-1825 (2013) - [j2]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka:
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. IEICE Trans. Electron. 96-C(8): 1076-1082 (2013) - [j1]Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka:
A study on micro level traffic prediction for energy-aware routers. ACM SIGOPS Oper. Syst. Rev. 47(3): 26-33 (2013) - [c4]Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka:
2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. CCNC 2013: 97-105 - 2012
- [c3]Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue:
Deterministic High Density Packet-Buffer System for Low Cost Network Systems. AINA 2012: 951-956 - [c2]Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki:
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. CICC 2012: 1-4 - [c1]Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue:
A slice structure using the management of network traffic prediction for green IT. HPSR 2012: 250-255
Coauthor Index
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