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2020 – today
- 2024
[j17]Juan Encinas
, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads. Microprocess. Microsystems 107: 105050 (2024)- [j16]Junjiao Sun, Jorge Portilla, Andrés Otero:
A Deep Learning Approach for Fear Recognition on the Edge Based on Two-Dimensional Feature Maps. IEEE J. Biomed. Health Informatics 28(7): 3973-3984 (2024) - [c34]Daniel Vázquez, Alfonso Rodríguez, Andrés Otero:
Open-Source Elastic CGRA Generator. CF (Companion) 2024 - [i3]Daniel Vázquez, Jose Miranda, Alfonso Rodríguez, Andrés Otero, Pasquale Davide Schiavone, David Atienza:
STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems. CoRR abs/2404.12503 (2024) - 2023
- [j15]José L. Núñez-Yáñez, J. Andrés Otero, Eduardo de la Torre:
Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. Microprocess. Microsystems 98: 104801 (2023) - [c33]Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez:
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. ARC 2023: 260-274 - [c32]Sara Casao, Andrés Otero, Álvaro Serra-Gómez, Ana C. Murillo, Javier Alonso-Mora, Eduardo Montijano:
A Framework for Fast Prototyping of Photo-realistic Environments with Multiple Pedestrians. ICRA 2023: 9083-9089 - [i2]Sara Casao, Andrés Otero, Álvaro Serra-Gómez, Ana C. Murillo, Javier Alonso-Mora, Eduardo Montijano:
A Framework for Fast Prototyping of Photo-realistic Environments with Multiple Pedestrians. CoRR abs/2304.07059 (2023) - [i1]José L. Núñez-Yáñez, Andrés Otero, Eduardo de la Torre:
Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite. CoRR abs/2304.08211 (2023) - 2022
- [j14]Alfonso Rodríguez, Andrés Otero, Marco Platzner, Eduardo de la Torre:
Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Trans. Computers 71(11): 2903-2914 (2022) - [c31]Javier Laserna, Andrés Otero, Eduardo de la Torre:
A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution. ARC 2022: 47-61 - [c30]Daniel Vázquez, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. DCIS 2022: 1-6 - [c29]Rafael Zamacola, Andrés Otero, Alfonso Rodríguez, Eduardo de la Torre:
Just-In-Time Composition of Reconfigurable Overlays (Invited Talk). PARMA-DITAM@HiPEAC 2022: 2:1-2:13 - 2021
- [j13]Rodrigo Marino, Cristian Wisultschew, Andrés Otero, José Manuel Lanza-Gutiérrez, Jorge Portilla, Eduardo de la Torre:
A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT. IEEE Internet Things J. 8(6): 4339-4352 (2021) - [j12]Rafael Zamacola, Andrés Otero, Eduardo de la Torre:
Multi-grain reconfigurable and scalable overlays for hardware accelerator composition. J. Syst. Archit. 121: 102302 (2021) - [c28]Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems. DCIS 2021: 1-7 - 2020
- [j11]Arturo Perez, Alfonso Rodríguez, Andrés Otero, David González Arjona, Álvaro Jiménez-Peralo, Miguel Ángel Verdugo, Eduardo de la Torre:
Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation. IEEE Access 8: 59891-59905 (2020) - [j10]Leonardo Suriano, Andrés Otero, Alfonso Rodríguez, Manuel Sánchez-Renedo, Eduardo de la Torre:
Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs. IEEE Access 8: 118707-118724 (2020) - [j9]Rafael Zamacola, Andrés Otero, Alberto García-Martínez, Eduardo de la Torre:
An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems. IEEE Access 8: 202133-202152 (2020) - [c27]Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. ARC 2020: 45-60
2010 – 2019
- 2019
- [c26]Cristian Wisultschew, Andrés Otero, Jorge Portilla, Eduardo de la Torre:
Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification. DCIS 2019: 1-7 - [c25]Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. FCCM 2019: 307 - [c24]Alberto García Ortiz, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems. ReCoSoC 2019: 20-26 - [c23]Alejandro G. Gener, Juan Valverde, J. Andrés Otero, Philip J. Harris:
A Fast Prototyping Workflow for Reconfigurable SDR Applications. ReCoSoC 2019: 66-73 - 2018
- [j8]Alberto García Ortiz, Alfonso Rodríguez, Raúl Guerra, Sebastián López, Andrés Otero, Roberto Sarmiento, Eduardo de la Torre:
A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. Remote. Sens. 10(11): 1790 (2018) - [j7]Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre:
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. Sensors 18(6): 1877 (2018) - [c22]Arturo Perez, Andrés Otero, Eduardo de la Torre:
Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics. AHS 2018: 51-58 - [c21]Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. ReConFig 2018: 1-8 - 2017
- [c20]Arturo Perez, Leonardo Suriano, Andrés Otero, Eduardo de la Torre:
Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems. AHS 2017: 40-47 - 2016
- [j6]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Teresa Riesgo, Roberto Sarmiento:
A scalable H.264/AVC deblocking filter architecture. J. Real Time Image Process. 12(1): 81-105 (2016) - 2015
- [j5]Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger:
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. 9(1): 1-13 (2015) - [c19]Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC 2015: 1-7 - 2014
- [j4]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems 38(8): 899-910 (2014) - [c18]Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL 2014: 1-4 - 2013
- [j3]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers 62(8): 1481-1493 (2013) - [c17]Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP 2013: 182-189 - [c16]Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP 2013: 351-352 - [c15]Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A self-adaptive image processing application based on evolvable and scalable hardware. FPL 2013: 1 - [c14]Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo:
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops 2013: 182-191 - [c13]Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
A scalable evolvable hardware processing array. ReConFig 2013: 1-7 - 2012
- [j2]Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors 12(3): 2667-2692 (2012) - [c12]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL 2012: 547-550 - [c11]Christian Pilato, Andrea Cazzaniga, Gianluca Durelli, Andrés Otero, Donatella Sciuto, Marco D. Santambrogio:
On the automatic integration of hardware accelerators into FPGA-based embedded systems. FPL 2012: 607-610 - [c10]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig 2012: 1-6 - [c9]Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. ReConFig 2012: 1-8 - 2011
- [c8]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS 2011: 184-191 - [c7]Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS 2011: 336-343 - [c6]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto Sarmiento:
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. FPL 2011: 369-375 - [c5]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Roberto Sarmiento, Teresa Riesgo:
A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. ICME 2011: 1-6 - [c4]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo:
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig 2011: 164-169 - 2010
- [j1]Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer:
Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. Int. J. Distributed Sens. Networks 6(1) (2010) - [c3]Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Generic Systolic Array for Run-Time Scalable Cores. ARC 2010: 4-16 - [c2]Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD 2010: 88-95 - [c1]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva:
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL 2010: 70-76
Coauthor Index
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last updated on 2024-10-07 22:08 CEST by the dblp team
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