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2020 – today
- 2022
[c9]Inkyung Kim, Daehee Kim, Sunyoung Kwon, Sheayun Lee, Jaekoo Lee:
Fall Detection using Biometric Information Based on Multi-Horizon Forecasting. ICPR 2022: 1364-1370
2010 – 2019
- 2018
- [j5]Jin-Yong Choi, Eyee Hyun Nam, Yoon Jae Seong, Jinhyuk Yoon, Sookwan Lee
, Hongseok Kim, Jeongsu Park, Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min:
HIL: A Framework for Compositional FTL Development and Provably-Correct Crash Recovery. ACM Trans. Storage 14(4): 36:1-36:29 (2018) - [c8]Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min:
FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDs. DAC 2018: 115:1-115:6 - 2017
- [j4]Hongseok Kim, Eyee Hyun Nam, JiHyuck Yun, Sheayun Lee, Sang Lyul Min:
P-BMS: A Bad Block Management Scheme in Parallelized Flash Memory Storage Devices. ACM Trans. Embed. Comput. Syst. 16(5s): 140:1-140:19 (2017)
2000 – 2009
- 2008
- [j3]Sheayun Lee, Insik Shin, Woonseok Kim, Insup Lee, Sang Lyul Min:
A design framework for real-time embedded systems with code size and energy constraints. ACM Trans. Embed. Comput. Syst. 7(2): 18:1-18:27 (2008) - 2007
- [j2]Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min:
Selective code transformation for dual instruction set processors. ACM Trans. Embed. Comput. Syst. 6(2): 10 (2007) - 2006
- [c7]Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo:
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. CODES+ISSS 2006: 235-240 - 2004
- [c6]Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min:
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. SCOPES 2004: 244-258 - 2003
- [c5]Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson:
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. SCOPES 2003: 33-48 - [c4]Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min:
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. WCET 2003: 91-94 - 2001
- [c3]Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang:
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors. LCTES/OM 2001: 1-10 - [c2]Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang:
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors. OM@PLDI 2001: 1-10
1990 – 1999
- 1999
- [j1]Sheayun Lee, Sang Lyul Min, Chong-Sang Kim, Chang-Gun Lee, Minsuk Lee:
Cache-Conscious Limited Preemptive Scheduling. Real Time Syst. 17(2-3): 257-282 (1999) - 1998
- [c1]Sheayun Lee, Chang-Gun Lee, Minsuk Lee, Sang Lyul Min, Chong-Sang Kim:
Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems. LCTES 1998: 51-64
Coauthor Index
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