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ORCIDYoshinobu Higami
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2020 – today
- 2024
[j29]Xihong Zhou, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi:
Testing and Delay-Monitoring for the High Reliability of Memory-Based Programmable Logic Device. IEICE Trans. Inf. Syst. 107(1): 60-71 (2024)- [c59]Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen:
Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. ITC-Asia 2024: 1-6 - 2023
- [j28]Senling Wang
, Xihong Zhou, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Test Point Insertion for Multi-Cycle Power-On Self-Test. ACM Trans. Design Autom. Electr. Syst. 28(3): 46:1-46:21 (2023) - [c58]Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni:
SASL-JTAG: A Light-Weight Dependable JTAG. DFT 2023: 1-3 - 2022
- [c57]Tsutomu Inamoto, Tomoki Nishino, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi:
Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation. GCCE 2022: 561-565 - 2020
- [j27]Tsutomu Inamoto, Yoshinobu Higami:
Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1456-1463 (2020) - [j26]Hanan T. Al-Awadhi, Tomoki Aono, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST. IEICE Trans. Inf. Syst. 103-D(11): 2289-2301 (2020)
2010 – 2019
- 2018
- [j25]Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima:
Automotive Functional Safety Assurance by POST with Sequential Observation. IEEE Des. Test 35(3): 39-45 (2018) - [j24]Keiichi Endo, Gakuto Fujioka, Ayame Onoyama, Dai Okano, Yoshinobu Higami, Shinya Kobayashi:
Evaluation of educational applications in terms of communication delay between tablets with Bluetooth or Wi-Fi Direct. Vietnam. J. Comput. Sci. 5(3-4): 219-227 (2018) - [c56]Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. ATS 2018: 155-160 - [c55]Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262. ETS 2018: 1-2 - 2017
- [j23]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 385-394 (2017) - [j22]Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. IEICE Trans. Inf. Syst. 100-D(9): 2224-2227 (2017) - [j21]Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi:
Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2842-2850 (2017) - [c54]Keiichi Endo, Ayame Onoyama, Dai Okano, Yoshinobu Higami, Shin-ya Kobayashi:
Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications. ACIIDS (1) 2017: 345-354 - [c53]Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi:
Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD). ATS 2017: 17-22 - [c52]Tsutomu Inamoto, Yoshinobu Higami:
Harnessing Fuzziness of the Pragmatic Rule-Design Without IF-THEN Rules. FSDM 2017: 54-62 - [c51]Yuuya Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yoshinobu Higami, Hiroshi Takahashi:
On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects. ISCIT 2017: 1-5 - 2016
- [j20]Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. IPSJ Trans. Syst. LSI Des. Methodol. 9: 13-20 (2016) - [c50]Kamoliddin Mavlonov, Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Design and Implementation of Data Synchronization and Offline Capabilities in Native Mobile Apps. ACIIDS (2) 2016: 61-71 - [c49]Kosuke Yamaguchi, Tsutomu Inamoto, Keiichi Endo, Yoshinobu Higami, Shinya Kobayashi:
Evaluation of Influence Exerted by a Malicious Group's Various Aims in the External Grid. ACS 2016: 112-122 - [c48]Senling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima:
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation. ATS 2016: 209-214 - [c47]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Road-Map to Bridge Theoretical and Practical Approaches for Elevator Operations. IIAI-AAI 2016: 1097-1102 - 2015
- [c46]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Giving formal roles to elevators for breaking symmetry in static elevator operation problems. GCCE 2015: 621-625 - [c45]Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis of Delay Faults Considering Hazards. ISVLSI 2015: 503-508 - 2014
- [j19]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs. Int. J. Netw. Comput. 4(2): 321-335 (2014) - [c44]Kamoliddin Mavlonov, Yoshinobu Higami, Shin-ya Kobayashi:
Sushi: A Lightweight Distributed Image Storage System for Mobile and Web Services. ACS 2014: 121-137 - [c43]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Decreasing computational times for solving static elevator operation problems by assuming maximum waiting times. GCCE 2014: 593-596 - [c42]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. ISVLSI 2014: 320-325 - [c41]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
A call-based integer programming model for static elevator operation problems. SCIS&ISIS 2014: 365-369 - 2013
- [j18]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment. IEICE Trans. Inf. Syst. 96-D(6): 1323-1331 (2013) - [c40]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja:
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. Asian Test Symposium 2013: 79-84 - [c39]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Injecting speculation on ideal trajectories into a trip-based integer programming model for elevator operations. GCCE 2013: 23-27 - [c38]Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi:
Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs. CANDAR 2013: 252-256 - 2012
- [j17]Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo:
Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool. IEICE Trans. Inf. Syst. 95-D(4): 1093-1100 (2012) - [j16]Dewiani, Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi:
Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks. J. Networks 7(9): 1441-1448 (2012) - [c37]Dewiani, Kouji Hirata, Yoshinobu Higami, Shin-ya Kobayashi:
Dynamic routing and wavelength assignment in multifiber WDM networks with sparse wavelength conversion. ICTC 2012: 567-572 - [c36]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis for Bridging Faults on Clock Lines. PRDC 2012: 135-144 - 2011
- [c35]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Fault simulation and test generation for clock delay faults. ASP-DAC 2011: 799-805 - [c34]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
On Detecting Transition Faults in the Presence of Clock Delay Faults. Asian Test Symposium 2011: 1-6 - [c33]Yoshinobu Higami, Hiroshi Furutani, Takao Sakai, Shuichi Kameyama, Hiroshi Takahashi:
Test Pattern Selection for Defect-Aware Test. Asian Test Symposium 2011: 102-107 - [c32]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Enhancement of Clock Delay Faults Testing. ETS 2011: 216 - 2010
- [j15]Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi:
Dynamic Parallel Downloading with Network Coding in $\lambda$-Grid Networks. J. Commun. 5(5): 425-435 (2010) - [j14]Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi:
Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks. J. Commun. 5(9): 692-702 (2010)
2000 – 2009
- 2009
- [j13]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3128-3135 (2009) - [j12]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. Inf. Media Technol. 4(4): 727-739 (2009) - [j11]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. IPSJ Trans. Syst. LSI Des. Methodol. 2: 250-262 (2009) - [c31]Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium 2009: 301-306 - [c30]Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu:
Diagnostic test generation for transition faults using a stuck-at ATPG tool. ITC 2009: 1-9 - [c29]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90 - [c28]Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96 - 2008
- [j10]Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki:
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Trans. Inf. Syst. 91-D(3): 675-682 (2008) - [j9]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Trans. Inf. Syst. 91-D(3): 690-699 (2008) - [j8]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Post-BIST Fault Diagnosis for Multiple Faults. IEICE Trans. Inf. Syst. 91-D(3): 771-775 (2008) - [j7]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3506-3513 (2008) - [c27]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. ATS 2008: 97-102 - 2007
- [c26]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. ATS 2007: 39-44 - [c25]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. ATS 2007: 271-274 - [c24]Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu:
Timing-Aware Diagnosis for Small Delay Defects. DFT 2007: 223-234 - [c23]Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251 - [c22]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design 2007: 781-786 - [p4]Yuji Kinoshita, Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi:
Development of Concealing the Purpose of Processing for Programs in a Distributed Computing Environment. Advances in Information Processing and Protection 2007: 263-269 - [p3]Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi:
A Consideration of Processor Utilization on Multi-Processor System. Advances in Information Processing and Protection 2007: 383-390 - [p2]Michihiko Kudo, Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi:
Reliability of Node Information on Autonomous Load Distribution Method. Advances in Information Processing and Protection 2007: 391-398 - 2006
- [j6]Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu:
On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Trans. Inf. Syst. 89-D(11): 2748-2755 (2006) - [c21]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC 2006: 659-664 - [c20]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
Diagnosis of Transistor Shorts in Logic Test Environment. ATS 2006: 354-359 - [c19]Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109 - 2005
- [j5]Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu:
Test cost reduction for logic circuits: Reduction of test data volume and test application time. Syst. Comput. Jpn. 36(6): 69-83 (2005) - [c18]T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu:
On the fault diagnosis in the presence of unknown fault models using pass/fail information. ISCAS (3) 2005: 2987-2990 - [p1]Koichi Kashiwagi, Yoshinobu Higami, Shin-ya Kobayashi:
Improvement of the processors operating ratio in task scheduling using the deadline method. Enhanced Methods in Computer Security, Biometric and Artificial Intelligence Systems 2005: 387-394 - 2004
- [j4]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu:
Generation of Test Sequences with Low Power Dissipation for Sequential Circuits. IEICE Trans. Inf. Syst. 87-D(3): 530-536 (2004) - [c17]Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu:
Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49 - [c16]Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu:
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Asian Test Symposium 2004: 216-221 - [c15]Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu:
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Asian Test Symposium 2004: 222-227 - 2003
- [c14]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz:
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397- - 2002
- [c13]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu:
A Method to Reduce Power Dissipation during Test for Sequential Circuits. Asian Test Symposium 2002: 326-331 - [c12]Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu:
Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. DELTA 2002: 431-433 - 2001
- [c11]Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu:
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63- - [c10]Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu:
Test Generation for Double Stuck-at Faults. Asian Test Symposium 2001: 71-75 - 2000
- [j3]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electron. Test. 16(5): 443-451 (2000) - [j2]Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita:
Static test compaction for IDDQ testing of bridging faults in sequential circuits. Syst. Comput. Jpn. 31(11): 41-50 (2000) - [c9]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514 - [c8]Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita:
Test sequence compaction for sequential circuits with reset states. Asian Test Symposium 2000: 165-170
1990 – 1999
- 1999
- [c7]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146 - [c6]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita:
Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design 1999: 72-77 - 1998
- [c5]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita:
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium 1998: 312-317 - 1997
- [c4]Yoshinobu Higami, Kozo Kinoshita:
Design of partially parallel scan chain. ED&TC 1997: 626 - 1996
- [c3]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99 - 1995
- [j1]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Partial scan design and test sequence generation based on reduced scan shift method. J. Electron. Test. 7(1-2): 115-124 (1995) - [c2]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium 1995: 169-175 - 1994
- [c1]Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC 1994: 624-630
Coauthor Index
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