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Ping-Ying Wang
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2010 – 2019
- 2015
- [c12]Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang:
A 1V fractional-N PLL with nonlinearity-insensitive modulator. A-SSCC 2015: 1-4 - [c11]Che-Fu Liang, Ping-Ying Wang:
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. ISSCC 2015: 1-3 - 2014
- [c10]Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang:
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO. ISSCC 2014: 270-271 - 2012
- [j2]Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu:
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 148-152 (2012) - 2011
- [c9]Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng:
An all-digital built-in self-test technique for transfer function characterization of RF PLLs. DATE 2011: 359-364 - 2010
- [c8]Ping-Ying Wang, Chia-Huang Fu:
All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL. ESSCIRC 2010: 270-273
2000 – 2009
- 2009
- [j1]Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang:
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. IEEE J. Solid State Circuits 44(8): 2182-2192 (2009) - 2008
- [c7]Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh:
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. CICC 2008: 749-752 - [c6]Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan:
A fractional spur reduction technique for RF TDC-based all digital PLLs. ESSCIRC 2008: 422-425 - [c5]Ping-Ying Wang, Hsiu-Ming Chang:
A charge pump-based direct frequency modulator. ISCAS 2008: 1962-1965 - [c4]Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh:
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. ISSCC 2008: 200-201 - 2007
- [c3]Ping-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang:
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. ISSCC 2007: 254-600 - 2006
- [c2]Ping-Ying Wang, C.-H. Chou, Hsueh-Wu Kao:
Chaos in delay locked loop. ISCAS 2006 - 2005
- [c1]Ping-Ying Wang, Hsiang Ji Hsieh, Yung-Yu Lin, Meng-Ta Yang, Hsueh-Wu Kao:
A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives. ISCAS (5) 2005: 5007-5010
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