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楊家驤
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2020 – today
- 2024
[j42]Po-Shao Chen
, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang:
A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring. IEEE J. Solid State Circuits 59(6): 1899-1911 (2024)- [j41]Tzu-Wei Tong, Tai-Jung Chen, Yi-Yen Hsieh, Chia-Hsiang Yang:
A 73.8k-Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition. IEEE J. Solid State Circuits 59(10): 3357-3365 (2024) - [j40]Yu-Hsuan Tsai, Yi-Cheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Shi-Hao Chen, Chi-Shi Chen, Chia-Hsiang Yang:
A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices. IEEE J. Solid State Circuits 59(11): 3816-3826 (2024) - [j39]Wen-Cong Huang, I-Ting Lin, Ying-Sheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality. IEEE J. Solid State Circuits 59(11): 3840-3852 (2024) - [j38]Yu-Cheng Lin, Ren-Hao Chiou, Chia-Hsiang Yang:
A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1878-1888 (2024) - [c53]Tang Lee, Ting-Yang Chen, I-Hsuan Liu, Chia-Hsiang Yang:
2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems. ISSCC 2024: 46-48 - [c52]Yi-Chen Chu, Yu-Cheng Lin, Yu-Chen Lo, Chia-Hsiang Yang:
30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization. ISSCC 2024: 488-490 - [c51]Chun-Wei Chang, I-Ting Lin, Chia-Hsiang Yang:
A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices. VLSI Technology and Circuits 2024: 1-2 - [c50]Ping-Sheng Wu, Yu-Cheng Lin, Chia-Hsiang Yang:
A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-Based Speculation. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j37]Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang:
A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction. IEEE J. Solid State Circuits 58(1): 167-176 (2023) - [j36]Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang:
A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator. IEEE J. Solid State Circuits 58(2): 520-529 (2023) - [j35]Sheng-Jung Yu, Yu-Chi Lee, Liang-Hsin Lin, Chia-Hsiang Yang:
An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices. IEEE J. Solid State Circuits 58(6): 1810-1819 (2023) - [j34]Chung-Hsuan Yang, Yi-Chung Wu, Yen-Lung Chen, Chao-Hsi Lee, Jui-Hung Hung, Chia-Hsiang Yang:
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping. IEEE Trans. Biomed. Circuits Syst. 17(6): 1331-1341 (2023) - [c49]Tzu-Wei Tong, Yi-Yen Hsieh, Tai-Jung Chen, Chia-Hsiang Yang:
A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition. A-SSCC 2023: 1-3 - [c48]Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang:
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. ISSCC 2023: 44-45 - [c47]I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots. ISSCC 2023: 46-47 - [c46]Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. ISSCC 2023: 332-333 - [c45]Liang-Hsin Lin, Zih-Sing Fu, Po-Shao Chen, Bo-Yin Yang, Chia-Hsiang Yang:
A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing. VLSI Technology and Circuits 2023: 1-2 - [c44]Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang:
A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing. VLSI Technology and Circuits 2023: 1-2 - [c43]Yi-Lin Lo, Yu-Chen Lo, Chia-Hsiang Yang:
A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j33]Chen-Chien Kao, Chiao-En Chen, Chia-Hsiang Yang:
Hybrid Precoding Baseband Processor for 64 × 64 Millimeter Wave MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1765-1773 (2022) - [j32]Ying-Sheng Lin, Yi-Pao Wu, Yi-Chung Wu, Pei-Lin Lee, Chia-Hsiang Yang:
Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal. IEEE J. Biomed. Health Informatics 26(11): 5473-5481 (2022) - [c42]Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang:
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction. ISSCC 2022: 1-3 - [c41]Chen-Chien Kao, Yi-Yen Hsieh, Chao-Hung Chen, Chia-Hsiang Yang:
Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression. MWSCAS 2022: 1-4 - [c40]Zih-Sing Fu, Yu-Chi Lee, Alex Park, Chia-Hsiang Yang:
A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training. VLSI Technology and Circuits 2022: 40-41 - [c39]Wen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality. VLSI Technology and Circuits 2022: 42-43 - [c38]Yu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang:
A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing. VLSI Technology and Circuits 2022: 74-75 - 2021
- [j31]Chieh Chung, Chia-Hsiang Yang:
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots. IEEE J. Solid State Circuits 56(1): 112-122 (2021) - [j30]Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang:
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. IEEE J. Solid State Circuits 56(1): 123-135 (2021) - [j29]Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification. IEEE J. Solid State Circuits 56(10): 3062-3076 (2021) - [j28]Yen-Lung Chen, Bo-Yi Chang, Chia-Hsiang Yang, Tzi-Dar Chiueh:
A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome. IEEE Trans. Parallel Distributed Syst. 32(6): 1465-1478 (2021) - [c37]Shuo-An Huang, Yi-Yen Hsieh, Chia-Hsiang Yang:
Design optimization for ADMM-Based SVM Training Processor for Edge Computing. AICAS 2021: 1-5 - [c36]Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang:
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. A-SSCC 2021: 1-3 - [c35]Sheng-Jung Yu, Yu-Chi Lee, Chia-Hsiang Yang:
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices. A-SSCC 2021: 1-3 - [c34]Yi-Lin Lo, Chia-Hsiang Yang:
A Color Doppler Processing Engine with an Adaptive Clutter Filter for Portable Ultrasound Imaging Devices. ICASSP 2021: 7893-7897 - [c33]Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang:
4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images. ISSCC 2021: 66-68 - 2020
- [j27]Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang:
A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control. IEEE J. Solid State Circuits 55(2): 452-464 (2020) - [j26]Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang:
A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices. IEEE J. Solid State Circuits 55(8): 2247-2258 (2020) - [j25]Yung-Jen Lin, Yu-Chi Lee, Hao-Min Liu, Herming Chiueh, Tai-Shih Chi, Chia-Hsiang Yang:
A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement. IEEE Trans. Circuits Syst. 67-I(12): 4984-4993 (2020) - [c32]Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition. A-SSCC 2020: 1-4 - [c31]Yao-Pin Wang, Chi-Chih Wen, Chen-Chien Kao, Chung-Jung Huang, Der-Zheng Liu, Chia-Hsiang Yang:
Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax. GLOBECOM 2020: 1-6 - [c30]Yi-Yen Hsieh, Yu-Chi Lee, Chia-Hsiang Yang:
A CycleGAN Accelerator for Unsupervised Learning on Mobile Devices. ISCAS 2020: 1-5 - [c29]Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang:
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. ISSCC 2020: 322-324 - [c28]Chieh Chung, Chia-Hsiang Yang:
21.2 A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots. ISSCC 2020: 324-326 - [c27]Herming Chiueh, Chia-Hsiang Yang, Charles H.-P. Wen, Chao-Guang Yang, Po-Hao Chien, Ching-Yang Hung, Yu-Jui Chen, Yao-Pin Wang, Chin-Fong Chiu, Jer Lin:
Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS. VLSI-DAT 2020: 1-2 - [c26]Chia-Hsiang Yang:
AI Acceleration with RISC-V for Edge Computing. VLSI-DAT 2020: 1 - [c25]Chi-Chih Wen, Yu-Chi Lee, Yi-Chung Wu, Chen-Chien Kao, Chia-Hsiang Yang:
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j24]Yu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang:
A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals. IEEE J. Solid State Circuits 54(10): 2907-2916 (2019) - [j23]Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu:
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem. IEEE Trans. Biomed. Eng. 66(11): 3156-3167 (2019) - [j22]Yan-Tong Chen, Wei-Cheng Sun, Chung-Chao Cheng, Tsung-Lin Tsai, Yeong-Luh Ueng, Chia-Hsiang Yang:
An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1205-1218 (2019) - [j21]Wei-Cheng Sun, Yu-Chieh Su, Yeong-Luh Ueng, Chia-Hsiang Yang:
An LDPC-Coded SCMA Receiver With Multi-User Iterative Detection and Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3571-3584 (2019) - [j20]Wei-Cheng Sun, Yan-Tong Chen, Chia-Hsiang Yang, Yeong-Luh Ueng:
Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems. IEEE Trans. Signal Process. 67(6): 1636-1647 (2019) - [c24]Yu-Chi Lee, Tai-Shih Chi, Chia-Hsiang Yang:
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices. AICAS 2019: 97-101 - [c23]Cheng-Hsun Lu, Yi-Chung Wu, Chia-Hsiang Yang:
A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training. A-SSCC 2019: 65-68 - [c22]Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang:
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. VLSI-DAT 2019: 1-4 - [i2]Shuo-An Huang, Chia-Hsiang Yang:
A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing. CoRR abs/1907.09916 (2019) - 2018
- [j19]Tsung-Hsien Lin, Chia-Hsiang Yang, Seung-Tak Ryu:
Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 53(10): 2739-2740 (2018) - [j18]Ting-I Chou, Kwuang-Han Chang, Jia-Yin Jhang, Shih-Wen Chiu, Guoxing Wang, Chia-Hsiang Yang, Herming Chiueh, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang:
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1365-1369 (2018) - [j17]Chun-Yu Yeh, Ting-Chung Chu, Chiao-En Chen, Chia-Hsiang Yang:
A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3918-3928 (2018) - [c21]Chih-Hsuan Chiang, Shuo-An Huang, Chiao-En Chen, Chia-Hsiang Yang:
A 2×2-16×16 Reconfigurable GGMD Processor for MIMO Communication Systems. ISCAS 2018: 1-5 - [c20]Chia-Hsiang Yang:
Massive MIMO detection VLSI design. VLSI-DAT 2018: 1 - [c19]Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang:
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control. VLSI Circuits 2018: 259-260 - [c18]Yu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang:
A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. VLSI Circuits 2018: 261-262 - 2017
- [j16]Mao-Ruei Li, Chia-Hsiang Yang, Yeong-Luh Ueng:
A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 52(2): 592-604 (2017) - [j15]Yi-Chung Wu, Chia-Hua Chang, Jui-Hung Hung, Chia-Hsiang Yang:
A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing. IEEE Trans. Biomed. Circuits Syst. 11(6): 1216-1225 (2017) - [j14]Yu-Cheng Tsai, Chiao-En Chen, Chia-Hsiang Yang:
A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 446-456 (2017) - [c17]Hsin-Tzu Lin, Yi-Chung Wu, Ping-Hsuan Hsieh, Chia-Hsiang Yang:
Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables. ISCAS 2017: 1-4 - [c16]Yi-Chung Wu, Jui-Hung Hung, Chia-Hsiang Yang:
14.8 A 135mW fully integrated data processor for next-generation sequencing. ISSCC 2017: 252-253 - [c15]Wei-Cheng Sun, Chia-Hsiang Yang, Yen-Ming Chen, Yeong-Luh Ueng:
An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors. VTC Spring 2017: 1-7 - 2016
- [j13]Chia-Hua Chang, Min-Te Chou, Yi-Chung Wu, Ting-Wei Hong, Yun-Lung Li, Chia-Hsiang Yang, Jui-Hung Hung:
sBWT: memory efficient implementation of the hardware-acceleration-friendly Schindler transform for the fast biological sequence mapping. Bioinform. 32(22): 3498-3500 (2016) - [j12]Cheng-Yen Lee, Ping-Hsuan Hsieh, Chia-Hsiang Yang:
A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 70-79 (2016) - [c14]Ting-I Chou, Shih-Wen Chiu, Kwuang-Han Chang, Yi-Ju Chen, Chen-Ting Tang, Chung-Hung Shih, Chih-Cheng Hsieh, Meng-Fan Chang, Chia-Hsiang Yang, Herming Chiueh, Kea-Tiong Tang:
Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease. BioCAS 2016: 592-595 - [c13]Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou:
Error-resilient sequential cells with successive time borrowing for stochastic computing. ICASSP 2016: 6545-6549 - 2015
- [j11]Chia-Hsiang Yang, Yi-Hsin Shih, Herming Chiueh:
An 81.6 µW FastICA Processor for Epileptic Seizure Detection. IEEE Trans. Biomed. Circuits Syst. 9(1): 60-71 (2015) - [j10]Chia-Hsiang Yang, Chun-Wei Chou, Chia-Shen Hsu, Chiao-En Chen:
A Systolic Array Based GTD Processor With a Parallel Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1099-1108 (2015) - [j9]Wei-Cheng Sun, Wei-Hsuan Wu, Chia-Hsiang Yang, Yeong-Luh Ueng:
An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2512-2522 (2015) - [j8]Chiao-En Chen, Yu-Cheng Tsai, Chia-Hsiang Yang:
An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems. IEEE Trans. Wirel. Commun. 14(1): 343-352 (2015) - [c12]Wei-Hsuan Wu, Wei-Cheng Sun, Chia-Hsiang Yang, Yeong-Luh Ueng:
A 794Mbps 135mW iterative detection and decoding receiver for 4×4 LDPC-coded MIMO systems in 40nm. VLSIC 2015: 102- - 2014
- [j7]Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu:
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. IEEE J. Solid State Circuits 49(1): 232-247 (2014) - [j6]Shih-Wen Chiu, Jen-Huo Wang, Kwuang-Han Chang, Ting-Hau Chang, Chia-Min Wang, Chia-Lin Chang, Chen-Ting Tang, Chien-Fu Chen, Chung-Hung Shih, Han-Wen Kuo, Li-Chun Wang, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu, Kea-Tiong Tang:
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia. IEEE Trans. Biomed. Circuits Syst. 8(6): 765-778 (2014) - [j5]Chia-Hsiang Yang, Ting-Ying Huang, Mao-Ruei Li, Yeong-Luh Ueng:
A 5.4 µW Soft-Decision BCH Decoder for Wireless Body Area Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2721-2729 (2014) - [j4]Chung-Chao Cheng, Jeng-Da Yang, Huang-Chang Lee, Chia-Hsiang Yang, Yeong-Luh Ueng:
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2738-2746 (2014) - [c11]Kea-Tiong Tang, Shih-Wen Chiu, Chung-Hung Shih, Chia-Ling Chang, Chia-Min Yang, Da-Jeng Yao, Jen-Huo Wang, Chien-Ming Huang, Hsin Chen, Kwuang-Han Chang, Chih-Cheng Hsieh, Ting-Hau Chang, Meng-Fan Chang, Chia-Min Wang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu:
24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia. ISSCC 2014: 420-421 - 2013
- [c10]Li-Lan Wang, Chia-Hsiang Yang, Herming Chiueh:
A 191μW BPSK demodulator for data and power telemetry in biomedical implants. ACM Great Lakes Symposium on VLSI 2013: 119-124 - [c9]Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu:
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. ISSCC 2013: 286-287 - [c8]Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou:
Power and area reduction in multi-stage addition using operand segmentation. VLSI-DAT 2013: 1-4 - [i1]Chiao-En Chen, Chia-Hsiang Yang:
An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems. CoRR abs/1311.0433 (2013) - 2012
- [j3]Chia-Hsiang Yang, Tsung-Han Yu, Dejan Markovic:
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example. IEEE J. Solid State Circuits 47(3): 757-768 (2012) - [j2]Tsung-Han Yu, Chia-Hsiang Yang, Danijela Cabric, Dejan Markovic:
A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios. IEEE J. Solid State Circuits 47(9): 2235-2245 (2012) - [c7]Yi-Hsin Shih, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh:
Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection. APSIPA 2012: 1-4 - 2011
- [c6]Tsung-Han Yu, Chia-Hsiang Yang, Dejan Markovic, Danijela Cabric:
An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing. GLOBECOM 2011: 1-6 - [c5]Fang-Li Yuan, Chia-Hsiang Yang, Dejan Markovic:
A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection. GLOBECOM 2011: 1-6
2000 – 2009
- 2009
- [j1]Chia-Hsiang Yang, Dejan Markovic:
A Flexible DSP Architecture for MIMO Sphere Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(10): 2301-2314 (2009) - [c4]Chia-Hsiang Yang, Dejan Markovic:
A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS. ESSCIRC 2009: 344-347 - 2008
- [c3]Chia-Hsiang Yang, Dejan Markovic:
A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications. GLOBECOM 2008: 3297-3301 - [c2]Chia-Hsiang Yang, Dejan Markovic:
A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels. ICC 2008: 725-731 - 2004
- [c1]Chia-Hsiang Yang, Yu-Hsuan Lin, Shih-Chun Lin, Tzi-Dar Chiueh:
Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems. ISCAS (4) 2004: 125-128
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Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
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Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
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Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
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Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
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OpenAlex data
Load additional information about publications from 
.
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last updated on 2025-01-09 13:26 CET by the dblp team
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