"Vertical integration after stacking (ViaS) process for low-cost and ..."

Kuniaki Sueoka et al. (2015)

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DOI: 10.1109/3DIC.2015.7334608

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Kuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii:
Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration. 3DIC 2015: TS8.3.1-TS8.3.5

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