"Parallel implementation of AES on 2.5D multicore platform with hardware ..."

Jielin Wang et al. (2015)

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DOI: 10.1109/ASICON.2015.7517001

access: closed

type: Conference or Workshop Paper

metadata version: 2018-08-28

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Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng:
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON 2015: 1-4

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