default search action
"A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA ..."
Kris Tiri, Ingrid Verbauwhede (2004)
- Kris Tiri, Ingrid Verbauwhede:
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. DATE 2004: 246-251
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.