"FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a ..."

J. Javier Martínez et al. (2005)

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DOI: 10.1109/FPL.2005.1515782

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-04

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J. Javier Martínez, F. Javier Toledo, F. Javier Garrigós, José Manuel Ferrández de Vicente:
FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach. FPL 2005: 547-550

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