"An Improved High Resolution CMOS Timing Generator Using Array of Digital ..."

Balaji Srinivasan, Vinay Bhaskar Chandratre (2010)

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DOI: 10.1109/VLSI.DESIGN.2010.37

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Balaji Srinivasan, Vinay Bhaskar Chandratre:
An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2010: 335-338

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