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"Analysis of Logic Gates for Generation of Switching Sequence in Symmetric ..."
Kanike Vinod Kumar, R. Saravana Kumar (2019)
- Kanike Vinod Kumar, R. Saravana Kumar:
Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter. IEEE Access 7: 97719-97731 (2019)
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