"Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process."

Fei Ma et al. (2011)

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DOI: 10.1016/J.MICROREL.2011.07.028

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type: Journal Article

metadata version: 2024-10-06

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Fei Ma, Yan Han, Bo Song, Shurong Dong, Meng Miao, Jianfeng Zheng, Jian Wu, Kehan Zhu:
Substrate-engineered GGNMOS for low trigger voltage ESD in 65 nm CMOS process. Microelectron. Reliab. 51(12): 2124-2128 (2011)

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